Preliminary
Application Notes
RF2690
Voltage Gain Measurement Set-up
The evaluation board uses a unity voltage gain Op-Amp to simulate the 60kΩ differential load impedance condition for
the chip. The 50Ω output impedance of Op-Amp makes the use of a 50Ω spectrum analyzer power measurement possi-
ble. The power gain measured will be considered as RAW Gain. The input impedance of the chip is 500Ω differential by
adding a parallel 680Ω resistor. The input transformer matches 50Ω to 500Ω and results in 10dB difference between
voltage gain and power gain, hence, the voltage gain of the chip is RAW Gain minus 10dB. Because the input trans-
former loss is 0.8dB, it needs to be added to the gain. Since the Op-Amp has the unity voltage gain, the voltage at the
evaluation board output is the same as the voltage at chip I or Q output. Therefore, the voltage gain of the chip with 60kΩ
load can be calculated by
Gv=RAW Gain-10+0.8(dB)
Input IP3 Measurement
The input IP3 measurement is based on a two tone inter-modulation test condition from the 3GPP standard, which spec-
ifies two tones with offset frequencies at 10MHz and 20MHz. Due to the on-chip baseband filtering, the two tone output
is attenuated and cannot be seen. Since the only parameter observable is the IM3 product, the input IP3 then is calcu-
lated by
IIP3=Pin+0.5*(Pin+RAW Gain-IM3)
Noise Figure Measurement
The noise figure measurement is based on the noise figure definition NF=N
O
-N
I
-Gain, where N
O
is the output noise
density, N
I
is the input noise density (-174dBm/Hz when no input signal is applied) and Gain is the RAW Gain. The out-
put noise density N
O
is measured at 1MHz offset when no signal input is applied. The NF is calculated by NF=N
O
-
174dBm/Hz-RAW Gain. Since the I and Q re-combination will provide 3dB extra for signal-to-noise ratio, the actual
noise figure is should be reduced by 3dB. In addition, noise figure should be reduced by the input transformer loss of
0.8dB. Therefore, the NF is calculated by
NF=N
O
+174-RAW Gain-3-0.8(dB)
1dB Gain Compression Point Voltage at Baseband Output
The device has a relatively constant 1dB gain compression point versus V
GC
. Gain compression is tested with a CW sig-
nal with 60kΩ load differential.
How to Calculate the Power Gain of the Demodulator
In the system analysis for cascaded gain, noise and IP, it is often required to calculate the power gain of the demodulator
chip itself in matched load condition. Below is an example on how to determine this power gain value.
For this example, the load impedance is 60kΩ differential, the output AC impedance of the I or Q port is 500Ω, the mea-
sured RAW Gain is 95dB.
First, the power gain from the input of the chip to the input of Op-Amp needs to be calculated. Since the voltage at the
50Ω load and the voltage at Op-Amp input are the same, the difference of the power gain across the Op-Amp is the ratio
of load impedances. Hence, the power gain to the Op-Amp input is 95dB-10log(60000/50)=95-30=65dB.
Second, the power gain of the demodulator itself with matched load is calculated. The mismatch coefficient a is deter-
mined by the mismatch coefficient equation
7
QUADRATURE
DEMODULATORS
4R
S
R
L
4
⋅
500
⋅
60000
-
α
= 10 log
-------------------------
= 10 log
-------------------------------------
= – 15dB
2
2
(
R
S
+
R
L
)
(
500 + 60000
)
Rev A4 010918
7-45
RFMD [ RF MICRO DEVICES ]
