RF5110G
Dissipated Power=P
DISS
=P_DC–P
OUT
R
TH
=R
TH_JC_RF5110G
+R
TH_SYSTEM_BOARD
(R
TH_JC_RF5110G
=25.6°C/W)
Junction Temperature @ 85°C ambient=T
J
=85°C+P
DISS
xR
TH
Efficiency calculation alone may not suffice, as the system board may be substantially thicker than that of the RF5110G evalu-
ation board. This will increase R
TH
for the system, and likewise T
J
.
Layout considerations are important in repeating RF5110G evaluation board performance in a system design. Via arrange-
ment underneath the part is critical, as are other via arrangements and supply trace routings (see “GSM Applications” section
for the GSM case). Layout files for the RF5110G evaluation board can be obtained by contacting RFMD applications/sales.
As already stated, output match is a primary consideration in achieving desired performance. In moving from the RF5110G
evaluation board to the system board, the first approach would be to implement the same matching topology/values as seen in
application schematics. Performance on the system board can then be checked, particularly with regard to gain and efficiency
at target output power. If needed, matching values can be adjusted to obtain equivalent performance. Observing each output
match from 150MHz to 900MHz, it can be seen that topology takes 1 of 2 possible configurations:
C – L – C: 150MHz, 220MHz, 900MHz
L – C: 450MHz
Other areas which impact response are the 1st and 2nd interstage matches, found at pins 1 and 5/6, respectively. Small sig-
nal responses for each match are shown in this data sheet. Checking response on the system board will verify that input/inter-
stage matches are in line (output to some extent as well). This verification can be done by placing SMA connectors at the
input/output of RF5110G, and observing small signal response.
Following the guidelines contained within this section should ensure successful implementation of RF5110G in general radio
applications.
GSM Applications
The RF5110G is a three-stage device with 32 dB gain at full power. Therefore, the drive required to fully saturate the output is
+3dBm. Based upon HBT (Heterojunction Bipolar Transistor) technology, the part requires only a single positive 3V supply to
operate to full specification. Power control is provided through a single pin interface, with a separate Power Down control pin.
The final stage ground is achieved through the large pad in the middle of the backside of the package. First and second stage
grounds are brought out through separate ground pins for isolation from the output. These grounds should be connected
directly with vias to the PCB ground plane, and not connected with the output ground to form a so called “local ground plane”
on the top layer of the PCB. The output is brought out through the wide output pad, and forms the RF output signal path.
The amplifier operates in near Class C bias mode. The final stage is “deep AB”, meaning the quiescent current is very low. As
the RF drive is increased, the final stage self-biases, causing the bias point to shift up and, at full power, draws about 2000mA.
The optimum load for the output stage is approximately 2.6Ω. This is the load at the output collector, and is created by the
series inductance formed by the output bond wires, vias, and microstrip, and 2 shunt capacitors external to the part. The opti-
mum load impedance at the RF Output pad is 2.6-j1.5Ω. With this match, a 50Ω terminal impedance is achieved. The input is
internally matched to 50Ω with just a blocking capacitor needed. This data sheet defines the configuration for GSM operation.
The input is DC coupled; thus, a blocking cap must be inserted in series. Also, the first stage bias may be adjusted by a resis-
tive divider with high value resistors on this pin to V
PC
and ground. For nominal operation, however, no external adjustment is
necessary as internal resistors set the bias point optimally.
V
CC
1 and V
CC
2 provide supply voltage to the first and second stage, as well as provides some frequency selectivity to tune to
the operating band. Essentially, the bias is fed to this pin through a short microstrip. A bypass capacitor sets the inductance
seen by the part, so placement of the bypass cap can affect the frequency of the gain peak. This supply should be bypassed
individually with 100pF capacitors before being combined with V
CC
for the output stage to prevent feedback and oscillations.
Rev A4 DS071026
7628 Thorndike Road, Greensboro, NC 27409-9421 · For sales or technical
support, contact RFMD at (+1) 336-678-5570 or sales-support@rfmd.com.
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