R2025S/D
Register Settings
•
Control Register 1 (ADDRESS Eh)
D7
D6
D5
D4
D3
D2
D1
D0
WALE
DALE
/CLEN2
TEST
CT2
CT1
CT0
(For Writing)
/12⋅24
WALE
DALE
/CLEN2
TEST
CT2
CT1
CT0
(For Reading)
/12⋅24
0
0
0
0
0
0
0
0
Default Settings *)
*) Default settings: Default value means read / written values when the PON bit is set to “1” due to VDD
power-on from 0 volts.
(1) WALE, DALE
WALE,DALE
0
1
Alarm_W Enable Bit, Alarm_D Enable Bit
Description
Disabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers).
Enabling the alarm interrupt circuit (under the control of the settings
of the Alarm_W registers and the Alarm_D registers)
(Default)
(2) /12⋅24
/12⋅24
/12-24-hour Mode Selection Bit
(Default)
Description
0
Selecting the 12-hour mode with a.m. and p.m. indications.
1
Selecting the 24-hour mode
Setting the /12⋅24 bit to 0 and 1 specifies the 12-hour mode and the 24-hour mode, respectively.
24-hour mode
12-hour mode
24-hour mode
00
12 (AM12)
12
01
01 (AM 1)
13
02
02 (AM 2)
14
03
03 (AM 3)
15
04
04 (AM 4)
16
05
05 (AM 5)
17
06
06 (AM 6)
18
07
07 (AM 7)
19
08
08 (AM 8)
20
09
09 (AM 9)
21
10
10 (AM10)
22
11
11 (AM11)
23
Setting the /12⋅24 bit should precede writing time data
12-hour mode
32 (PM12)
21 (PM 1)
22 (PM 2)
23 (PM 3)
24 (PM 4)
25 (PM 5)
26 (PM 6)
27 (PM 7)
28 (PM 8)
29 (PM 9)
30 (PM10)
31 (PM11)
(3) /CLEN2
/CLEN2
32-kHz Clock Output Bit2
Description
0
Enabling the 32-kHz clock output
(Default)
1
Disabling the 32-kHz clock output
Setting the /CLEN2 bit or the /CLEN1 bit (D3 in the control register 2) to 0 specifies generating clock pulses
with the oscillation frequency of the 32.768-kHz crystal oscillator for output from the 32KOUT pin.
Conversely, setting both the /CLEN1 and the /CLEN2 bit to 1 specifies disabling (“L”) such output.
(4) TEST
TEST
Test Bit
Description
(Default)
0
Normal operation mode.
1
Test mode.
The TEST bit is used only for testing in the factory and should normally be set to 0.
11
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
