RS5C313
2. Register
2.1 Control Register (at Eh)
D3
CTFG
CTFG
D2
12/24
12/24
D1
WTEN
XSTP
D0
ADJ
BSY
(For write operation)
(For read operation)
±30-second Adjustment Bit
ADJ
Description
0
1
Ordinary operation
Second digit adjustment
Clock/Calendar Counter Busy-state Indication Bit
BSY
Description
0
1
Ordinary operation
Second digit carry or adjustment
Clock Counter Enable/Disable Setting Bit
WTEN
Description
0
1
Disabling of 1-second digit carry for clock counter
Enabling of 1-second digit carry for clock counter
Oscillator Halt Sensing Bit
XSTP
Description
0
1
Ordinary oscillation
Oscillator halt sensing
12/24-hour Time Display System Selection Bit
12/24
Description
0
1
12-hour time display system (separate for mornings and afternoons)
24-hour time display system
Interrupt Flag Bit
CTFG
Description
0
1
INTR=H(Nch Open Drain). Enabling of write operation when the CT3 bit is set to 1.
INTR=L (Nch Open Drain). Enabling of write operation when the CT3 bit is set to 1.
2.1-1 (ADJ)
When the ADJ bit is set to 1: (If the WTEN bit is 0, adjustment of second digits is started after the WTEN bit is set to 1.)
1) For second digits ranging from 00 to 29 seconds: Time counts smaller than seconds are reset to set second digits to “00”.
2) For second digits ranging from 30 to 59 seconds: Time counts smaller than seconds are reset to set second digits to “00”
and increment minute digits by 1. After the ADJ bit is set to 1, the BSY
bit is set to 1 for the maximum duration of 122.1µs.
8
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
