RS5C313
2.2 Interrupt Cycle Register (at 7h)
D3
CT3
CT3
D2
CT2
CT2
D1
CT1
CT1
D0
CT0
CT0
(For write operation)
(For read operation)
1
*
Bits for selecting the interrupt cycle and output mode at the INTR pin
1) (CT3 to CT0)
*
The CT3 to CT0 bits are used to select the interrupt cycle and output mode at the INTR pin. There are two interrupt modes selectable: the pulse mode
(when the CT3 bit is set to 0) and the level mode (when the CT3 bit is set to 1).
The interrupt cycle and output mode at the INTR pin are shown in detail in the section on the CTFG bit in “2.1 Control Register (at Eh)”.
2.3 Test Register (at Fh)
D3
D2
D1
D0
TEST
0
(For write operation)
*
0
*
0
*
0
1
*
(For read operation)
Bit For Testing*2
TEST
Description
0
1
Testing mode
Ordinary operating mode
1) The TEST bit is write-only and set to 0 when read.
*
*
2) The TEST bit should be fixed at 1 for ordinary operation and will automatically be set to 1 when the CE pin is at the low level.
11
RICOH [ RICOH ELECTRONICS DEVICES DIVISION ]
