BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS
Technical Note
●Operating
description
(1) Data clear
When the reset terminal (CLR, CLB) is set to “L”, the content of all latch circuits are set to “H”, and all parallel outputs are
initialised.
(For model with reset terminal only)
(2) Data transfer
Serial data is sequentially input to the shift register during the rise of the clock time (strobe signal is not active). When
the strobe signal is active, the content of the shift register are transferred to the latch circuit.
(3) Cascade connection
Serial input data is output from the serial output through the shift register, regardless of the strobe signal.
(except
for
BU2050F,
BU2092F/BU2092FV)
●Application
circuit
C1
(*)
VDD
P1 P2
VDD
Serial data input
Clock input
Strobe input
Latch input
Pn-2 Pn-1 Pn
MPU
VSS
VSS
Serial data output
P1 P2
VDD
Serial data input
Clock input
Strobe input
Latch input
Pn-2 Pn-1 Pn
VSS
Serial data output
(*C1 must be placed as close to the terminal as possible.)
Fig. 1
BU2092F/BU2092FV
Q0�½�Q11
OUT
●Interfaces
BU2050F
DATA, CLOCK, STB, CLR
V
DD
V
DD
BU2050F
P1�½�P8
BU2092F/BU2092FV
DATA, CLOCK, LCK, OE
V
DD
V
DD
INPUT
OUTPUT
IN
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
BU2099FV
DATA, CLOCK, LCK, OE
V
DD
V
DD
V
DD
BU2099FV
Q0�½�Q11
OUT
BU2099FV
SO
V
DD
BU2152FS
CLOCK, DATA, STB, CLB
V
DD
V
DD
V
DD
IN
OUT
(only OE pin)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
GND(VSS)
BU2152FS
P1�½�P28
V
DD
V
DD
V
DD
BU2152FS
SO
V
DD
V
DD
VSS
VSS
VSS
GND(VSS)
GND(VSS) GND(VSS)
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6/24
2009.06 - Rev.A
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