BU2092F-E2 参数 Datasheet PDF下载

BU2050F,BU2092F,BU2092FV,BU2099FV,BD7851FP,BU2152FS

【BU2050F】

●Pin

descriptions

Pin No.

Pin Name

1

2

3

4

5

6

7

8

9

10

P3

P4

P5

V

SS

P6

P7

P8

DATA

CLK

STB

Serial Data Input

Parallel Data Output

GND

Parallel Data Output

Technical Note

Function

11

12

13

14

●Timing

chart

CLK

CLR

P1

P2

V

DD

Clock Signal Input

Strobe Signal Input

In case of “L”, the data of shift register outputs.

In case of “H”, all parallel outputs and data of latch circuit do not change.

Reset Signal Input

In case of “L”, the data of latch circuit reset, and all parallel output (P1�½�P8) can be L.

Normally CLR=H

Parallel Data output

Power Supply

DATA

DATA8

DATA7

DATA6

DATA2

DATA1

CLR

STB

Pn

Previous DATA

DATA

“L”

Fig. 2

1. After the power is turned on and the voltage is stabilized, STB should be activated, after clocking 8 data bits into the

DATA pin.

th

2. Pn parallel output data of the shift register is set after the 8 clock by the STB.

3. Since the STB is level latch, data is retained in the “L” section and renewed in the “H” section of the STB.

［Function

explanation�½

・

A latch circuit has the reset function, which is common in all bits. In case of CLR terminal is “L”, the latch

circuit is reset non-synchronously without the other input condition, and all parallel output can be “L”.

・

A serial data inputted from DATA terminal is read in shift register with synchronized rising of clock.

In case of STB is “L” (CLR is ”H”), transmit the data which read in the shift register to latch circuit, and

outputs from the parallel data output terminal (P1�½�P8).

In case of STB is “H”, all parallel outputs and the data of latch do not change.

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2009.06 - Rev.A