SA9401
PCM Interface
The PCM Interface controls all aspects of the transfer of PCM signals onto the PCM
highway.
Eight-bit
Tone Registers
store the PCM tone samples and are updated once per PCM
frame. Before a PCM word is transmitted to the PCM highway the
Tone Selector
determines whether or not the Cadence controller requires an OFF period. If so then a
specific PCM word for Silence (held in the
Silence Register)
is substituted for the tone
sample.
The actual transfer of the tone (or silence) samples to the PCM highway is the function
of the
Injection Controller. Time Slot Registers
indicate to which PCM time-slot the
sample is to be injected. These registers (one for each tone stream) comprise 5 ad-
dress bits and one (high-order) enabling bit. A
Comparator
checks if the Time Slot
Register contents match the current PCM time-slot and if so feeds the Tone Sample (or
Silence Sample) into the
Parallel In Serial Out
module and the required sample is
clocked out via the PCM_OUT pin. The PCM_OUT pin is enabled only when samples
are being clocked out (ie when the 5 least significant bits of the Time Slot Register
matches the current PCM Time Slot and the Time Slot Register MSB is Low) and is
held in a tri-state condition at all other times.
Watchdog Timer
The watchdog timer performs a function completely independently of the Universal Tone
Generator. Its operation is described below.
The watchdog timer comprises three I/O pins, viz;
WD_EN - an active low input which enables/disables the watchdog.
WD_RST - a rising edge triggered input which resets the watchdog timer and
prevents the output from resetting the microprocessor.
WD_INT - an active low tri-state output which when active, resets a micro-
processor.
The watchdog timer operates as follows:
-
For the watchdog timer to operate, the WD_EN pin must be held low (i.e. active).
With the WD_EN pin held high, the WD_INT output remains tri-stated.
The delay between WD_EN going active and a WD_INT output is 2 seconds.
-
The timer is reset every time a rising edge is detected on the WD_RST pin. The
minimum pulse width of the WD_RST input is two CLKIN periods.
-
The WD_INT output comprises an active low pulse of 5 milliseconds followed by a
tri-state period of 1995 milliseconds (assuming no valid WD_RST pulse is detected
within 2 seconds of the previous WD_RST pulse).
The timing diagram for the Watchdog Timer is given in Figure 2. Note that although the
timebase for the Watchdog Timer is always 2048kHz, the WD-EN and WD-RST inputs
are strobed at the external clock rate.
7
sames
SAMES [ SAMES ]
