SA9401
PIN DESCRIPTION (Continued)
Pin No
37, 36, 35, 33,
32, 31, 30, 29
9, 14, 19
7
40
I/0
I
I
O
I
Designation
D0..D7
PS0, PS1,
PS2
CLKDIV2
CLK_SEL
Description
EPROM Data Lines
Program Select Inputs for Selecting
between 1 of 8 tone plans
CLKIN divided by 2 output (i.e. 4096 kHz or 1024
kHz depending on CLK_SEL input)
Selects between CKLIN of 8192 or 2048 kHz and
Synchronisation source.
0 = 8192kHz/Internal
1 = 2048kHz/External
Used for IC testing purpose. Tied Low during
normal operation.
Asynchronous Reset Pin. Resets all Internal Flip
Flops (active low)
Watchdog reset input (Rising-edge triggered) Tied
high if unused
Watchdog enable input (active low) Tied high if
unused
Watchdog output (active low, tri-state)
28
38
16
17
18
I
I
I
I
O
TEST
MRST
WD_RST
WD_EN
WD_INT
BLOCK DIAGRAM
CLKDIV2
/MRST
CLK_SEL
CLKIN
CLOCK
GENERATOR
2MCLK
8KFS
PCMFSC
WD_RST
WDENB
D[7 : 0]
WATCHDOG
TIMER
WD_INT
INTRUDE
TONE
GENERATOR
INTRFRQ
/FS1
CADENCE
TIMER
INTRCAD
PS[2 : 0]
EPROM
INTERFACE
A[13 : 0]
TEST
PCM
INTERFACE
SA9401
DR-01085
PCM_OU
sames
3
SAMES [ SAMES ]
