KM62256C Family
TIMING WAVEFORM OF WRITE CYCLE(1)
(WE Controlled)
CMOS SRAM
t
WC
Address
t
CW(2)
CS
t
AW
t
WP(1)
WE
t
AS(3)
Data in
t
WHZ
Data out
Data Undefined
t
DW
Data Valid
t
OW
t
DH
t
WR(4)
TIMING WAVEFORM OF WRITE CYCLE(2)
(CS Controlled)
t
WC
Address
t
AS(3)
CS
t
AW
t
WP(1)
WE
t
DW
Data in
Data Valid
t
DH
t
CW(2)
t
WR(4)
Data out
NOTES
(WRITE CYCLE)
High-Z
High-Z
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, t
WP
is measured from the begining of write
to the end of write.
2. t
CW
is measured from the CS going low to end of write.
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
R
applied in case a write ends as CS or WE going high.
W
DATA RETENTION WAVE FORM
CS controlled
V
CC
4.5V
t
SDR
Data Retention Mode
t
RDR
2.2V
V
DR
CS≥V
CC
- 0.2V
CS
GND
7
Revision 4.0
December 1997
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
