DDR SDRAM 512Mb C-die (x4, x8, x16)
DDR SDRAM
32M x 4Bit x 4 Banks / 16M x 8Bit x 4 Banks / 8M x 16Bit x 4 Banks Double Data Rate SDRAM
9.0 General Description
The K4H510438C / K4H510838C / K4H511638C is 536,870,912 bits of double data rate synchronous DRAM organized as 4x
33,554,432 / 4x 16,777,216 / 4x 8,388,608 words by 4/8/16bits, fabricated with SAMSUNG′s high performance CMOS technology. Syn-
chronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both
edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful
for a variety of high performance memory system applications.
10.0 Absolute Maximum Rating
Parameter
Voltage on any pin relative to V
SS
Voltage on V
DD
& V
DDQ
supply relative to V
SS
Storage temperature
Power dissipation
Short circuit current
Symbol
V
IN
, V
OUT
V
DD
, V
DDQ
T
STG
P
D
I
OS
Value
-0.5 ~ 3.6
-1.0 ~ 3.6
-55 ~ +150
1.5
50
Unit
V
V
°C
W
mA
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommend operation condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
11.0 DC Operating Conditions
Parameter
Recommended operating conditions(Voltage referenced to V
SS
=0V, T
A
=0 to 70°C)
Symbol
V
DD
V
DD
V
DDQ
V
DDQ
V
REF
V
TT
V
IH
(DC)
V
IL
(DC)
V
IN
(DC)
V
ID
(DC)
VI(Ratio)
I
I
I
OZ
I
OH
I
OL
I
OH
I
OL
Min
2.3
2.5
2.3
2.5
0.49*VDDQ
V
REF
-0.04
V
REF
+0.15
-0.3
-0.3
0.36
0.71
-2
-5
-16.8
16.8
-9
9
Max
2.7
2.7
2.7
2.7
0.51*VDDQ
V
REF
+0.04
V
DDQ
+0.3
V
REF
-0.15
V
DDQ
+0.3
V
DDQ
+0.6
1.4
2
5
Unit
Note
Supply voltage(for device with a nominal V
DD
of 2.5V for DDR266/333)
Supply voltage(for device with a nominal V
DD
of 2.6V for DDR400)
I/O Supply voltage(for device with a nominal V
DD
of 2.5V for DDR266/333)
I/O Supply voltage(for device with a nominal V
DD
of 2.5V for DDR400)
I/O Reference voltage
I/O Termination voltage(system)
Input logic high voltage
Input logic low voltage
Input Voltage Level, CK and CK inputs
Input Differential Voltage, CK and CK inputs
V-I Matching: Pullup to Pulldown Current Ratio
Input leakage current
Output leakage current
Output High Current(Normal strengh driver) ;V
OUT
= V
TT
+ 0.84V
Output High Current(Normal strengh driver) ;V
OUT
= V
TT
- 0.84V
Output High Current(Half strengh driver) ;V
OUT
= V
TT
+ 0.45V
Output High Current(Half strengh driver) ;V
OUT
= V
TT
- 0.45V
V
V
V
V
V
V
V
-
uA
uA
mA
mA
mA
mA
1
2
3
4
Note :
1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may
not exceed +/-2% of the dc value.
2. V
TT
is not applied directly to the device. V
TT
is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track vari-
ations in the DC level of VREF
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range,
for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers
due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to
source voltages from 0.1 to 1.0.
Rev. 1.1 June. 2005
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
