DDR SDRAM 512Mb C-die (x4, x8, x16)
6.0 Block Diagram (
32Mb x 4
/
16Mb x 8 / 8Mb x 16
I/O x4 Banks)
DDR SDRAM
x4/8/16
LWE
I/O Control
CK, CK
Data Input Register
Serial to parallel
LDM (x4x8)
LUDM (x16)
Bank Select
x8/16/32
16Mx8/ 8Mx16/ 4Mx32
Output Buffer
2-bit prefetch
Sense AMP
Refresh Counter
Row Buffer
Row Decoder
16Mx8/ 8Mx16/ 4Mx32
16Mx8/ 8Mx16/ 4Mx32
16Mx8/ 8Mx16/ 4Mx32
x8/16/32
x4/8/16
x4/8/16
DQi
Address Register
CK, CK
ADD
Column Decoder
LCBR
LRAS
Col. Buffer
Latency & Burst Length
Strobe
Gen.
DLL
Data Strobe
LCKE
Programming Register
LRAS LCBR
LWE
LCAS
LWCBR
CK, CK
LDM (x4x8)
LUDM (x16)
Timing Register
DM Input Register
CK, CK
CKE
CS
RAS
CAS
WE
LDM (x4x8)
LUDM (x16)
Rev. 1.1 June. 2005
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
