K4S643232C
CMOS SDRAM
512K x 32Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
• 3.3V power supply
The K4S643232C is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG¢s high performance CMOS technol-
ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
ORDERING INFORMATION
• Auto & self refresh
Part NO.
Max Freq. Interface Package
• 15.6us refresh duty cycle
K4S643232C-TC/L55
K4S643232C-TC/L60
K4S643232C-TC/L70
K4S643232C-TC/L80
K4S643232C-TC/L10
183MHz
166MHz
86
TSOP(II)
LVTTL
143MHz
125MHz
100MHz
FUNCTIONAL BLOCK DIAGRAM
LWE
Data Input Register
LDQM
Bank Select
512K x 32
512K x 32
512K x 32
512K x 32
DQi
CLK
ADD
Column Decoder
Latency & Burst Length
LCKE
Programming Register
LWCBR
LRAS
LCBR
LWE
LCAS
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
DQM
Samsung Electronics reserves the right to
change products or specification without
notice.
*
REV. 1.1 Nov. '99
- 3 -
SAMSUNG [ SAMSUNG ]
