K6X1008C2D Family
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS1=OE=V
IL
, CS2=WE=V
IH
)
t
RC
Address
t
OH
Data Out
Previous Data Valid
t
AA
CMOS SRAM
Data Valid
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
t
RC
Address
t
AA
t
CO1
CS
1
t
HZ(1,2)
CS
2
t
CO2
t
OE
t
OH
OE
t
OLZ
t
LZ
Data Valid
t
OHZ
Data out
NOTES (READ
CYCLE)
High-Z
1.
t
HZ
and
t
OHZ
are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition,
t
HZ
(Max.) is less than
t
LZ
(Min.) both for a given device and from device to device
interconnection.
6
Revision 1.0
September 2003