KM29W040AT 参数 Datasheet PDF下载

KM29W040AT, KM29W040AIT

System Interface Using CE don’ -care.

t

FLASH MEMORY

For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal

32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for

voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and read-

ing would provide significant savings in power consumption.

Figure 3. Program Operation with CE don’ -care.

t

CLE

CE don’-care

t

CE

≈

WE

ALE

I/O

0

~

7

80H

Start Add.(3Cycle)

Data Input

Data Input

≈

10H

t

CS

CE

(Max. 60ns)

t

CH

CE

t

CEA

t

REA

t

WP

WE

I/O

0

~

7

out

RE

Timing requirements : If CE is is exerted high during sequential

data-reading, the falling edge of CE to valid data(tCEA) must

be kept greater than 60ns.

Figure 4. Read Operation with CE don’ -care.

t

CLE

CE don’-care

t

CE

RE

ALE

R/B

t

R

WE

I/O

0

~

7

00H

Start Add.(3Cycle)

Data Output(sequential)

11

≈