PRELIMINARY
KM681000C Family
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
C
L
1)
CMOS SRAM
1. Including scope and jig capacitance
AC CHARACTERISTICS
Speed Bins
Parameter List
Symbol
Min
Read cycle time
Address access time
Chip select to output
Output enable to valid output
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
Chip select to end of write
Address set-up time
Address valid to end of write
Write
Write pulse width
Write recovery time
Write to output high-Z
Data to write time overlap
Data hold from write time
End write to output low-Z
t
RC
t
AA
t
CO1,
t
CO2
t
OE
t
LZ
t
OLZ
t
HZ
t
OHZ
t
OH
t
WC
t
CW
t
AS
t
AW
t
WP
t
WR1,
t
WR2
t
WHZ
t
DW
t
DH
t
OW
55
-
-
-
10
5
0
0
10
55
45
0
45
40
0
0
25
0
5
55ns
Max
-
55
55
25
-
-
20
20
-
-
-
-
-
-
-
20
-
-
-
Min
70
-
-
-
10
5
0
0
10
70
60
0
60
50
0
0
30
0
5
70ns
Max
-
70
70
35
-
-
25
25
-
-
-
-
-
-
-
25
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Units
DATA RETENTION CHARACTERISTICS
Item
Vcc for data retention
Symbol
V
DR
Test Condition
CS
1
1)
≥Vcc-0.2V,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V
KM681000CL
Data retention current
I
DR
Vcc=3.0V, CS
1
≥Vcc-0.2V,
CS2≥Vcc-0.2V or CS
2
≤0.2V
KM681000CL-L
KM681000CLI
KM681000CLI-L
Data retention set-up
Recovery time
t
SDR
t
RDR
See data retention waveform
Min
2.0
-
-
-
-
0
5
Typ
-
1
1
-
-
-
-
Max
5.5
20
10
25
10
-
-
ms
µA
Unit
V
1. CS
1
≥Vcc-0.2v,
CS
2
≥Vcc-0.2V
or CS
2
≤0.2V
5
Revision 2.0
November 1997
SAMSUNG [ SAMSUNG SEMICONDUCTOR ]
