PRELIMINARY
KM681000C Family
CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
1)
CL
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
1. Including scope and jig capacitance
AC CHARACTERISTICS
Speed Bins
Parameter List
Symbol
Units
55ns
70ns
Min
55
-
Max
Min
70
-
Max
Read cycle time
tRC
tAA
-
55
55
25
-
-
70
70
35
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
Chip select to output
Output enable to valid output
tCO1, tCO2
tOE
-
-
-
-
Read
Chip select to low-Z output
Output enable to low-Z output
Chip disable to high-Z output
Output disable to high-Z output
Output hold from address change
Write cycle time
tLZ
10
5
10
5
tOLZ
tHZ
-
-
0
20
20
-
0
25
25
-
tOHZ
tOH
0
0
10
55
45
0
10
70
60
0
tWC
-
-
Chip select to end of write
Address set-up time
tCW
-
-
tAS
-
-
Address valid to end of write
Write pulse width
tAW
45
40
0
-
60
50
0
-
tWP
-
-
Write
Write recovery time
tWR1,tWR2
tWHZ
tDW
-
-
Write to output high-Z
0
20
-
0
25
-
Data to write time overlap
Data hold from write time
End write to output low-Z
25
0
30
0
tDH
-
-
tOW
5
-
5
-
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
CS1 ³ Vcc-0.2V, CS2³ Vcc-0.2V or CS2£0.2V
Min
Typ
Max
5.5
20
10
25
10
-
Unit
1)
Vcc for data retention
VDR
2.0
-
1
1
-
V
KM681000CL
KM681000CL-L
KM681000CLI
KM681000CLI-L
-
-
Vcc=3.0V, CS1³ Vcc-0.2V,
CS2³ Vcc-0.2V or CS2£0.2V
Data retention current
IDR
mA
-
-
-
Data retention set-up
Recovery time
tSDR
tRDR
0
5
-
See data retention waveform
ms
-
-
1. CS1³ Vcc-0.2v, CS2³ Vcc-0.2V or CS2£0.2V
Revision 2.0
5
November 1997
SAMSUNG [ SAMSUNG ]
