KS0127B Data Sheet
MULTIMEDIA VIDEO
Table 1: Analog Video Input selections
INSEL[3:0](hex)
0
1
2
4
5
6
8
9
A
F
Selected Input(s)
AY0
AY1
AY2
AC0
AC1
AC2
AY0, AC0
AY1, AC1
AY2, AC2
AY2(Y), AC1(Cb), AC2(Cr)
Video Type
Composite
Composite
Composite
Composite
Composite
Composite
S-Video
S-Video
S-Video
YCbCr component video
1.1.2. Digital AGC Control
The AGC normally references to the ADC code difference between sync tip and back porch. Two sets of sync
tip-back porch ADC values are available for different AGC gain requirements: if
AGCGN
= 0, the sync tip locks to
code 2, and the back porch locks to code 70; when
AGCGN
= 1, the sync tip locks to 16, and the back porch locks
to code 70. Video signal with abnormal sync tip or very bright saturated colors may cause the ADC to limit the
maximum value. This situation can be corrected by enabling the
AGCOVF
bit in the
CMDB
register to force the
gain tracking loop to reduce AGC when maximum limiting conditions occur. The AGC may also be programmed to
freeze the AGC at the current value by setting the
AGCFRZ
bit in the
CMDB
register. Once the AGC is frozen, the
gain can be manually adjusted with the
AGC
register. The tracking time constant for the AGC can be controlled
with the
AGC_LPG[1:0]
bits in the
TRACKB
register. In addition, the AGC tracking time constant can be
configured as 2X faster during acquisition via the
AGC_LKG.
1.1.3. Digital Video Input
The high quality digital video down scaler in the KS0127B can be directly accessed via the EXV bi-directional port.
The KS0127B accepts CCIR 656 compliant 8-bit YCbCr digital video input with embedded or external timing. Video
timing may also be generated by the KS0127B. Data path for 8-bit YCbCr input is shown in Figure 3. Selection of
analog video input or digital CCIR 656 data is with the
INPSL[1:0]
register bits. The KS0127B can operate in
master or slave timing mode when the chip is programmed for digital video input.
1.1.4. Pixel Clock and Timing Mode Selection for Digital Video Input
Pixel clock and synchronization timing can be individually selected to either come from an external generator or be
generated internally. In addition, if synchronization is provided by an external source, the KS0127B supports
embedded syncs as defined in CCIR 656, or TTL HS and VS inputs. Selection of pixel clock is via
CKDIR
bit in
Modified on May/04/2000
ELECTRONICS
PAGE 9 OF 96
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