KS0127B Data Sheet
PIN DESCRIPTION (Continued)
Pin Name
EVAV(OENC1)
4
Pin #
Type
I/O
Description
MULTIMEDIA VIDEO
Valid line flag. Polarity is programmable. Active when output video
line is valid. During reset, the pin is an input and the logic state of
this pin is latched into the
OENC[1]register
bit. Use a 10 kΩ resistor
for pull-up or pull-down.
Odd field flag. Polarity is programmable. Active for fields 1 and 3.
PAL ID flag. High for phase alternating line.
Digital video data, timing and clock output 3-state control.
Pixel clock. In normal decoding mode, this is an output. When the
EXV port is used as an input, this can be programmed as an input
pixel clock.
Pixel output clock (rate is one half of CK) aligned to HAV signal.
Sliced VBI data output. Data can be from Closed Caption, Teletext,
Intercast, or WSS type encoded data.
When high, this pin indicates that valid VBI data is being clocked out
at the CCDAT pin or at the digital video output.
ODD
PID
OEN
CK
22
17
15
18
O
O
I
I/O
CK2
CCDAT
CCEN
21
73
74
O
O
O
MULTI-PURPOSE I/O PORTS AND TEST ENABLE
PORTA
SCH(PORTB)
TESTEN
TEST
58
24
57
96
I/O
I/O
I
I
Multi-purpose I/O port.
Multi-purpose I/O port.
When tied to VDD, the chip is put into the test mode. For normal use,
this pin should be connected to VSS.
When tied to VDD, the chip is put into the test mode. For normal use,
this pin should be connected to VSS.
REFERENCE AND COMPENSATION
VRT
VRB
COMP2
77
78
97
I/O
I/O
I/O
ADC VRT compensation (requires an external 0.1
µ
F capacitor
connected to VSS).
ADC VRB compensation (requires an external 0.1
µ
F capacitor
connected to VSS).
Internal 1.3 V reference (requires an external 0.1
µ
F capacitor
connected to VSS).
HOST INTERFACE
SCLK
SDAT
AEX0 - AEX1
75
72
69 - 70
I
I/O
I
Serial clock for IIC host interface.
Serial data for IIC host interface.
Device ID selection for IIC host interface.
Modified on May/04/2000
ELECTRONICS
PAGE 5 OF 96
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