LC89950
Electrical Characteristics at Ta = 25°C, V
= 5.0 V, Fscp = 15.625 kHz
DD
Switch States
Parameter
Symbol
min
typ
max
Unit
Test
conditions
SW1
SW2
SW3
SW4
Current drain
I
a/b
b
a
a
a/b
a/b
a/b
a/b
a/b
a
a/b
a/b
a/b
a/b
a/b
a
1
2
2
2
2
3
3
3
4
4
5
5
5
5
6
6
7
7
8
8
9
9
5
0.7
0.7
1.4
1.4
–2
10
15
2.7
2.7
3.4
3.4
+2
mA
V
DD
Output pin voltage (pin 1)
Output pin voltage (pin 3)
Input pin voltage (pin 7)
Input pin voltage (pin 5)
V
V
(R-Y)
1.7
1.7
2.4
2.4
0
OUT
(B-Y)
a
a
V
OUT
V
(R-Y)
(B-Y)
(R-Y)
(B-Y)
b
a
V
IN
V
a
a
V
IN
G
a
a
dB
V
Voltage gain
G
b
a
a
a
–2
0
+2
dB
V
Differential voltage gain
Frequency characteristics
∆G
a↔b
a
a
a
a
0.1
–1
0.3
dB
V
G (R-Y)
f
a
a
a
–3
–3
57
57
57
57
dB
G (B-Y)
f
b
a
a
a
–1
dB
+L6 (R-Y)
+L6 (B-Y)
–L6 (R-Y)
–L6 (B-Y)
Lclk (R-Y)
Lclk (B-Y)
No (R-Y)
No (B-Y)
a
a
a
b
60
63
63
63
63
12
12
2
%
Positive phase input linearity +L6
b
a
a
b
60
%
a
a
b
b
60
%
Inverted input linearity
Clock leakage (4 MHz)
Noise level
–L6
b
a
b
b
60
%
a
a
a
a
7
mVrms
mVrms
mVrms
mVrms
Ω
b
a
a
a
7
a
a
a
b
1
b
a
a
b
1
2
Z
(R-Y)
(B-Y)
a
a↔b
a↔b
a
a
a
200
200
300
300
63.80
63.80
400
400
OUT
Output impedance
Delay time
Z
b
a
a
Ω
OUT
Td (R-Y)
Td (B-Y)
a
a
a
µs
b
a
a
a
µs
Sandcastle Pulse (Input Clock) Conditions
Parameter
Symbol
Fscp
Conditions
min
typ
max
16.625
5.0
Unit
kHz
µs
V
Input frequency*1
Input pulse width
High level*2
14.625
3.0
15.625
4.0
TW bgp
Vhigh
Vmid
5.9
6.5
7.5
Mid level*3
2.5
3.5
4.4
V
Low level
Vlow
–0.3
0
2.5
V
Notes: 1. Indicates the synchronization range for the PLL circuit. The delay time changes with the input frequency.
2. Vhigh is the minimum value between c and d.
3. Vmid is the maximum value between a and b and between e and f.
No. 5440-2/5
SANYO [ SANYO SEMICON DEVICE ]
