Edge6420
HIGH-PERFORMANCE PRODUCTS – ATE
PIN Description
Ball Name
Ball Location
Description
VOUT_CH[0:3]_[0:4]
G13, G15, F14, F13, F15, G3, F1, F2, Group A DAC output volages for channels 0 to 3.
F3, E1, J3, J1, K2, K3, K1, J13, K15,
K14, K13, L15
VOUT_CH[0:3]_[5:6]
VOUT_CH[0:3]_[7:8]
E14, E15, E2, E3, L2, L1, L14, L13
Group B DAC output voltages for channels 0 to 3.
E13, D14, D1, D2, L3, M2, M15, M14 Group C DAC output voltaqges for channels 0 to 3.
VOUT_CH[0:3]_[9:10] D15, D13, D3, C1, M1, M3, M13, N15 Group D DAC output voltages for channels 0 to 3.
IOUT_CH[0:3]_[0:1]
IOUT_CH[0:3]_[2:4]
C15, C14, B1, C2, N1, N2, P15, N14 Group E DAC output voltages for channels 0 to 3.
H14, H15, G14, H3, G1, G2, H2, H1, Group F DAC output voltages for channels 0 to 3.
J2, H13, J15, J14
R_MASTER
P5
Master external resistor used to define the reference current
for the gain and offset setting block for voltage DACs.
R_GAIN_(A,B,C,D,E,F)
R_OFFSET_(A,B,C,D)
P11, R10, N10, P10, R9, N9
R6, P6, N6, R5
Pins for external resistor to set current gain for both voltage
and current output DACs.
Pins for external resistor to set the offset voltage for Group
A, B, C, and D voltage output DAC's.
SDI
CK
B10
A11
C6
Serial data input.
Clock for the input data shift register.
Strobe to transfer the shift register data to the DACs.
Chip enable.
UPDATE
CE
A10
Active low chip reset. Sets the DACs to a known default
state.
RESET*
C5
SDO
CK_OUT
SCAN_OUT
TEST_MODE
VREF
B5
Serial Data Out.
A6
B11
Regenerated clock output for daisy chain purposes.
Analog output test pin.
B6
Test mode pin for internal scan.
Reference input (for a 2.5V band gap).
Positive analog voltage supply.
Analog 5V supply.
C9
AVCC
C3, C12, N4, R12
C7, N7
AVDD
VEE
A9, R8, B9, P9
B8, N8
Negative analog voltage supply.
Analog ground (minimize noise).
Supply ground.
AGND
SGND
A8, R7
DVDD
B7, P7
Digital voltage supply.
DGND
C8, P8
Digital supply ground.
www .semtech.com
2000 Semtech Corp.
2
SEMTECH [ SEMTECH CORPORATION ]
