SC420
POWER MANAGEMENT
Pin Configuration
Top View
Ordering Information
Device
(1)
SC420IMLTR
Package
MLP-12
Temp Range (T
J
)
-40° to 125°C
PGND
12
N.C.
DRN
11
10
Note:
(1) Only available in tape and reel packaging. A reel
contains 3000 devices.
9
8
7
TG
BST
CO
1
2
3
BG
VIN
CDELAY
(
2) This device is ESD sensitive. Use of standard ESD
handling precautions is required.
4
5
6
(MLP-12)
Pin Descriptions
Pin
#
1
2
3
4
5
6
Pin
Name
TG
BST
CO
VIN2
EN
VPN
Pin Function
Output gate drive for the switching (high-side) MOSFET.
Bootstrap pin. A capacitor is connected between BST and DRN pins to develop the floating bootstrap
voltage for the high-side MOSFET. The capacitor value is typically between 0.1µF and 1µF (ceramic).
Logic level PWM input signal to the SC420 supplied by external controller.
Input power (VBAT) to the DC/DC converter. Used as supply reference for internal Combi-Sense
TM
circuitry. Connect as close as possible to Drain of TOP switching MOSFET.
Active high logic level input signal. A logic High enables TG and BG switching. A low level disables
outputs and reduces quiescent current to IQ
SD
Virtual Phase Node. Connect an RC between this pin and the output sense point to Enable Combi-
Sense
TM
operation.
7
The capacitance connected between this pin and GND sets the additional propagation delay for BG
CDELAY going low to TG going high. Total propagation delay =20ns + 1ns/pF. If no capacitor is connected, the
propragation delay = 20ns.
VIN
BG
PGND
N.C.
DRN
Input supply for the bottom drive and the Logic. A
1µF-10µF
Ceramic Capacitor must be connected
from this pin to PGND, placed less than 0.5" from SC420.
Output drive for the synchronous (bottom) MOSFET.
Ground. Keep this pin close to the synchronous MOSFETs source.
No Connect
This pin connects to the junction of the switching and synchronous MOSFETs . This pin can be subjected
to a -2V minimum relative to PGND without affecting operation.
5
United States Patent No. 6,441,597
www.semtech.com
VIN2
VPN
EN
8
9
10
11
12
©
2003 Semtech Corp.