SC420
POWER MANAGEMENT
Applications Information (Cont.)
be very close to each other, preferably with common PCB
copper land with multiple vias to the ground plane (if
used). The parallel Schottky (if used) must be physically
next to the Bottom FET’s drain and source pins. Any
trace or lead inductance in these connections will drive
current way from the Schottky and allow it to flow through
the FET’s Body diode, thus reducing efficiency.
Preventing Inadvertent Bottom FET Turn-on
At high VIN2 input voltages, (12V and greater) a fast turn-
on of the top FET creates a positive going spike on the
Bottom FET’s gate through the Miller capacitance, Crss
of the bottom FET. The voltage appearing on the gate
due to this spike is:
V
SPIKE
Vin
*
Crss
=
(
Crss
+
Ciss
)
mined by:
F
ring
=
1
1
=
( 2
Π
*
Sqrt
(
L
ST
*
Coss
)
2
π
L
ST
*
C
OSS
-Where:
L
st
= The effective stray inductance of the top FET added
to trace inductance of the connection between top FET’s
source and the bottom FET’s drain added to the trace
resistance of the bottom FET’s ground connection.
C
OSS
= Drain to source capacitance of bottom FET. If
there is a Schottky used, the capacitance of the Schottky
is added to this value.
Although this ringing does not pose any power losses due
to a fairly high Q, it could cause the phase node to go too
far negative, thus causing improper operation, double
pulsing or at worst driver damage. On the SC420, the
drain node, DRN, can go as far as 2V below ground with-
out affecting operation or sustaining damage.
The ringing is also an EMI nuisance due to its high reso-
nant frequency. Adding a capacitor, typically 1000-
2000pf, in parallel with Coss of the bottom FET will of-
ten eliminate the EMI issue.
Prevent Driver Overvoltage
The negative voltage spikes on the phase node adds to
the bootstrap capacitor voltage, thus increasing the volt-
age between VBST - VDRN.
This is of special importance
if higher boost voltages are used.
If the phase node
negative spikes are too large, the voltage on the boost
capacitor could exceed device’s absolute maximum rat-
ing of 7V. To eliminate the effect of the ringing on the
boost capacitor voltage, place a 4.7 - 10 Ohm resistor
between boost Schottky diode and V
IN
to filter the nega-
tive spikes on DRN Pin. Alternately, a Silicon diode, such
as the commonly available 1N4148 can substitute for
the Schottky diode and eliminate the need for the series
resistor.
Proper layout will guarantee minimum ringing and elimi-
nate the need for external components. Use of surface
mount MOSFETs, while increasing thermal resistance,
will reduce lead inductance as well as radiated EMI.
8
United States Patent No. 6,441,597
www.semtech.com
Where Ciss is the input gate capacitance of the bottom
FET. This is assuming that the impedance of the drive
path is too high compared to the instantaneous imped-
ance of the capacitors, since dV/dT and thus the effec-
tive frequency is very high. If the BG pin of the SC420 is
very close to the bottom FET, Vspike will be reduced de-
pending on trace inductance, rate of rise of current, etc.
A capacitor may be added from the gate of the Bottom
FET to its source, preferably less than 0.5in away. This
capacitor will be added to Ciss in the above equation to
reduce the effective spike voltage.
The bottom MOSFET must be selected with attention
paid to the Crss/Ciss ratio. A low ratio reduces the Miller
feedback and thus reduces Vspike. Also MOSFETs with
higher Turn-on threshold voltages will conduct at a higher
voltage and will not turn on during the spike. A zero ohm
bottom FET gate resistor will obviously help keeping the
gate voltage low during off time.
Ultimately, slowing down the top FET by adding gate re-
sistance will reduce di/dt which will in turn make the ef-
fective impedance of the capacitors higher, thus allow-
ing the BG driver to hold the bottom gate voltage low. It
does this at the expense of increased switching times
(and switching losses) for the top FET.
The top MOSFET source must be close to the bottom
MOSFET drain to prevent ringing and the possibility of
the phase node going negative. This frequency is deter-
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2003 Semtech Corp.
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