sharp
2.1 Data Protection
LHF80J01
8
3.3 Standby
CE# at a logic-high level (V
IH
) places the device in
standby mode which substantially reduces device power
consumption. DQ
0
-DQ
15
outputs are placed in a high-
impedance state independent of OE#. If deselected during
block erase, full chip erase, word/byte write or lock-bit
configuration, the device continues functioning, and
consuming active power until the operation completes.
When V
CCW
≤V
CCWLK
, memory contents cannot be
altered. The CUI, with two-step block erase, full chip
erase, word/byte write or lock-bit configuration command
sequences, provides protection from unwanted operations
even when high voltage is applied to V
CCW
. All write
functions are disabled when V
CC
is below the write
lockout voltage V
LKO
or when RP# is at V
IL
. The device’s
block locking capability provides additional protection
from inadvertent code or data alteration by gating block
erase, full chip erase and word/byte write operations.
Refer to Table 5 for write protection alternatives.
3.4 Reset
RP# at V
IL
initiates the reset mode.
In read modes, RP#-low deselects the memory, places
output drivers in a high-impedance state and turns off all
internal circuits. RP# must be held low for a minimum of
100ns. Time t
PHQV
is required after return from reset
mode until initial memory access outputs are valid. After
this wake-up interval, normal operation is restored. The
CUI is reset to read array mode and status register is set to
80H.
During block erase, full chip erase, word/byte write or
lock-bit configuration modes, RP#-low will abort the
operation. RY/BY# remains low until the reset operation
is complete. Memory contents being altered are no longer
valid; the data may be partially erased or written. Time
t
PHWL
is required after RP# goes to logic-high (V
IH
)
before another command can be written.
As with any automated device, it is important to assert
RP# during system reset. When the system comes out of
reset, it expects to read from the flash memory. Automated
flash memories provide status information when accessed
during block erase, full chip erase, word/byte write or
lock-bit configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization may not
occur because the flash memory may be providing status
information instead of array data. SHARP’s flash
memories allow proper CPU initialization following a
system reset through the use of the RP# input. In this
application, RP# is controlled by the same RESET# signal
that resets the system CPU.
3 BUS OPERATION
The local CPU reads and writes flash memory in-system.
All bus cycles to or from the flash memory conform to
standard microprocessor bus cycles.
3.1 Read
Information can be read from any block, identifier codes
or status register independent of the V
CCW
voltage. RP#
can be at V
IH
.
The first task is to write the appropriate read mode
command (Read Array, Read Identifier Codes or Read
Status Register) to the CUI. Upon initial device power-up
or after exit from reset mode, the device automatically
resets to read array mode. Six control pins dictate the data
flow in and out of the component: CE#, OE#, BYTE#,
WE#, RP# and WP#. CE# and OE# must be driven active
to obtain data at the outputs. CE# is the device selection
control, and when active enables the selected memory
device. OE# is the data output (DQ
0
-DQ
15
) control and
when active drives the selected memory data onto the I/O
bus. BYTE# is the device I/O interface mode control.
WE# must be at V
IH
, RP# must be at V
IH
, and BYTE#
and WP# must be at V
IL
or V
IH
. Figure 16, 17 illustrates
read cycle.
3.2 Output Disable
With OE# at a logic-high level (V
IH
), the device outputs
are disabled. Output pins (DQ
0
-DQ
15
) are placed in a
high-impedance state.
Rev. 1.27
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
