LHF80J01
10
sharp
The CUI does not occupy an addressable memory
location. It is written when WE# and CE# are active. The
address and data needed to execute a command are latched
on the rising edge of WE# or CE# (whichever goes high
first). Standard microprocessor write timings are used.
Figures 18 and 19 illustrate WE# and CE# controlled write
operations.
3.7 Write
Writing commands to the CUI enable reading of device
data and identifier codes. They also control inspection and
clearing of the status register. When V =2.7V-3.6V and
CC
V
=V
, the CUI additionally controls block
CCW
CCWH1/2
erase, full chip erase, word/byte write and lock-bit
configuration.
4 COMMAND DEFINITIONS
The Block Erase command requires appropriate command
data and an address within the block to be erased. The Full
Chip Erase command requires appropriate command data
and an address within the device. The Word/Byte Write
command requires the command and address of the
location to be written. Set Permanent and Block Lock-Bit
commands require the command and address within the
device (Permanent Lock) or block within the device
(Block Lock) to be locked. The Clear Block Lock-Bits
command requires the command and address within the
device.
When the V
voltage ≤V
, read operations from
CCW
CCWLK
the status register, identifier codes, or blocks are enabled.
Placing V on V enables successful block
CCWH1/2
CCW
erase, full chip erase, word/byte write and lock-bit
configuration operations.
Device operations are selected by writing specific
commands into the CUI. Table 3 defines these commands.
(1,2)
Table 2.1. Bus Operations (BYTE#=V )
IH
(3)
Mode
Notes
8
RP#
CE#
OE#
WE#
Address
V
DQ
D
RY/BY#
CCW
X
0-15
Read
V
V
V
V
X
X
X
X
X
X
X
IH
IL
IL
IH
OUT
Output Disable
Standby
V
V
V
V
X
X
X
High Z
IH
IL
IH
IH
V
V
X
X
X
X
High Z
High Z
IH
IH
Reset
4
8
V
X
High Z
High Z
X
IL
See
Figure 4, 5
Read Identifier Codes
Write
V
V
V
V
X
X
Note 5
IH
IL
IL
IH
6,7,8
V
V
V
V
X
D
IH
IL
IH
IL
IN
(1,2)
Table 2.2. Bus Operations (BYTE#=V )
IL
(3)
Mode
Read
Notes
8
RP#
CE#
OE#
WE#
Address
V
DQ
RY/BY#
CCW
X
0-7
V
V
V
V
X
X
X
X
D
X
X
IH
IL
IL
IH
OUT
Output Disable
Standby
V
V
V
V
X
X
X
High Z
High Z
High Z
IH
IL
IH
IH
V
V
X
X
X
X
X
IH
IH
Reset
4
8
V
X
High Z
IL
See
Figure 4, 5
Read Identifier Codes
V
V
V
V
X
X
Note 5
High Z
X
IH
IL
IL
IH
Write
6,7,8
V
V
V
V
X
D
IH
IL
IH
IL
IN
NOTES:
1. Refer to DC Characteristics. When V
≤V
, memory contents can be read, but not altered.
CCW
CCWLK
2. X can be V or V for control pins and addresses, and V
or V
for V
. See DC Characteristics for
IL
IH
CCWLK
CCWH1/2
CCW
V
voltages.
CCWLK
3. RY/BY# is V when the WSM is executing internal block erase, full chip erase, word/byte write or lock-bit configuration
OL
algorithms. It is High Z during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive),
word/byte write suspend mode or reset mode.
4. RP# at GND±0.2V ensures the lowest power consumption.
5. See Section 4.2 for read identifier code data.
6. Command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed
when V
=V
and V =2.7V-3.6V.
CCW
CCWH1/2 CC
7. Refer to Table 3 for valid D during a write operation.
IN
8. Never hold OE# low and WE# low at the same timing.
Rev. 1.27
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
