LH28F800SU
8M (512K × 16, 1M × 8) Flash Memory
56-PIN TSOP
TOP VIEW
INTRODUCTION
Sharp’s LH28F800SU 8M Flash Memory is a revolu-
tionary architecture which enables the design of truly
mobile, high performance, personal computing and com-
munication products. With innovative capabilities, 5 V
single voltage operation and very high read/write per-
formance, the LH28F800SU is also the ideal choice for
designing embedded mass storage flash memory sys-
tems.
The LH28F800SU is a very high density, highest per-
formance non-volatile read/write solution for solid-state
storage applications. Its symmetrically blocked archi-
tecture (100% compatible with the LH28F008SA 8M
Flash memory, the LH28F016SA 16M Flash memory
and the LH28F016SU 16M 5 V single voltage Flash
memory), extended cycling, low power 3.3 V operation,
very fast write and read performance and selective block
locking provide a highly flexible memory component suit-
able for high density memory cards, Resident Flash
Arrays and PCMCIA-ATA Flash Drives. The
LH28F800SU’s dual read voltage enables the design of
memory cards which can interchangeably be read/writ-
ten in 3.3 V and 5.0 V systems. Its x8/x16 architecture
allows the optimization of memory to processor inter-
face. The flexible block locking option enables bundling
of executable application software in a Resident Flash
Array or memory card. Manufactured on Sharp’s 0.55
µm ETOX™ process technology, the LH28F800SU is
the most cost-effective, high-density 3.3 V flash memory.
3/5
CE
1
NC
NC
A
19
A
18
A
17
A
16
V
CC
A
15
A
14
A
13
A
12
CE
0
V
PP
RP
A
11
A
10
A
9
A
8
GND
A
7
A
6
A
5
A
4
A
3
A
2
A
1
1
2
3
4
5
6
7
8
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56
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WP
WE
OE
RY/BY
DQ
15
DQ
7
DQ
14
DQ
6
GND
DQ
13
DQ
5
DQ
12
DQ
4
V
CC
GND
DQ
11
DQ
3
DQ
10
DQ
2
V
CC
DQ
9
DQ
1
DQ
8
DQ
0
A
0
BYTE
NC
NC
DESCRIPTION
The LH28F800SU is a high performance 8M
(8,388,608 bit) block erasable non-volatile random
access memory organized as either 512K × 16 or
1M × 8. The LH28F800SU includes sixteen 64K (65,536)
blocks or sixteen 32-KW (32,768) blocks. A chip memory
map is shown in Figure 3.
The implementation of a new architecture, with many
enhanced features, will improve the device operating
characteristics and results in greater product reliability
and ease of use.
Among the significant enhancements of the
LH28F800SU:
28F800SUR-17
Figure 2. TSOP Configuration
•
•
•
•
5 V Write/Erase Operation (5 V V
PP
)
3.3 V Low Power Capability (2.7 V V
CC
Read)
Improved Write Performance
Dedicated Block Write/Erase Protection
A 3/5
»
input pin reconfigures the device internally for
optimized 3.3 V or 5.0 V read/write operation.
2
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