Stacked Chip (16M Flash & 4M SRAM)
LRS1331
Table 1. Pin Descriptions
PIN
A
0
to A
16
F-A
17
to F-A
19
S-A
17
F-CE
S-CE
1
, S-CE
2
F-WE
S-WE
F-OE
S-OE
S-LB
S-UB
F-RP
DESCRIPTION
Address Inputs (Common)
Address Inputs (Flash)
Address Input (SRAM)
Chip Enable Input (Flash)
Chip Enable Inputs (SRAM)
Write Enable Input (Flash)
Write Enable Input (SRAM)
Output Enable Input (Flash)
Output Enable Input (SRAM)
SRAM Byte Enable Input (DQ
0
to DQ
7
)
SRAM Byte Enable Input (DQ
8
to DQ
15
)
Deep Power Down Input (Flash)
Block erase and Word Write: V
IH
Read: V
IH
Deep Power Down: V
IL
Write Protect Input (Flash)
Two Boot Blocks Locked: V
IL
Ready/Busy Output(Flash)
During an Erase or Write operation: V
OL
Block Erase and Word Write Suspend: HIGH-Z
Deep Power Down: V
OH
Data Input and Outputs (Common)
Power Supply (Flash)
Power Supply (SRAM)
Write, Erase Power Supply (Flash)
Block Erase and Word Write: F-V
PP
= V
PPLK
All Blocks Locked: F-V
PP
< V
PPLK
Ground (Flash)
Ground (SRAM)
No Connection
Test Pins (Should be Open)
TYPE
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
F-WP
Input
F-RY/BY
DQ
0
to DQ
15
F-V
CC
S-V
CC
F-V
PP
F-GND
S-GND
NC
T
1
to T
5
Output
Input/Output
Power
Power
Power
Power
Power
—
—
Data Sheet
3
SHARP [ SHARP ELECTRIONIC COMPONENTS ]
