IRF/B/S/SL4310
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W.
Period
V
GS
=10V
-
+
Circuit Layout Considerations
•
Low Stray Inductance
•
Ground Plane
•
Low Leakage Inductance
Current Transformer
*
D.U.T. I
SD
Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. V
DS
Waveform
Diode Recovery
dv/dt
-
-
+
R
G
•
•
•
•
dv/dt controlled by R
G
Driver same type as D.U.T.
I
SD
controlled by Duty Factor "D"
D.U.T. - Device Under Test
V
DD
V
DD
+
-
Re-Applied
Voltage
Body Diode
Forward Drop
Inductor
Curent
Inductor
Current
Ripple
≤
5%
I
SD
*
V
GS
= 5V for Logic Level Devices
Fig 21.
Peak Diode Recovery dv/dt Test Circuit
for N-Channel
HEXFET
®
Power MOSFETs
V
(BR)DSS
15V
tp
DRIVER
VDS
L
RG
V
GS
20V
D.U.T
IAS
tp
+
V
- DD
A
0.01
Ω
I
AS
Fig 22a.
Unclamped Inductive Test Circuit
L
D
V
DS
Fig 22b.
Unclamped Inductive Waveforms
V
DS
90%
+
V
DD
-
D.U.T
10%
V
GS
Pulse Width < 1µs
Duty Factor < 0.1%
V
GS
t
d(on)
t
r
t
d(off)
t
f
Fig 23a.
Switching Time Test Circuit
Fig 23b.
Switching Time Waveforms
Id
Vds
Vgs
L
VCC
0
DUT
1K
Vgs(th)
Qgs1 Qgs2
Qgd
Qgodr
Fig 24a.
Gate Charge Test Circuit
Fig 24b.
Gate Charge Waveform
7 / 11
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