SAB
SAB
SAF
SAF
2.6 Receive Data Flow (Summary)
82525
82526
82525
82526
The following figure gives an overview of the management of the received HDLC frames as
affected by different operating modes.
FLAG
MDS1 MDS0 ADM MODE
ADDR
CTRL
Ι
DATA
RFIFO
CRC
STATUS
FLAG
ADDRESS
CONTROL
RAH1, 2 RAL1, 2
0
0
1
Auto/16
RHCR
RSTA
RAL1, 2
0
0
0
Auto/8
X
RFIFO
RHCR
RSTA
RAH1, 2
0
1
1
Non
Auto/16
RAL1, 2
RFIFO
RHCR
RSTA
RAL1, 2
0
1
0
Non
Auto/8
X
RFIFO
RHCR
RSTA
RAH1, 2
RFIFO
1
0
1
Transparent 1
RAL1
RHCR
RSTA
RFIFO
1
0
0
Transparent 0
RAL1
RHCR
RSTA
Description of Symbols:
Compared with (register)
Processed autonomously
Stored (FIFO, register)
Note: In case of on 8 Bit Address,
the Control Field starts here!
ITD00228
Figure 8
Receive Data Flow of HSCX
Semiconductor Group
26
SIEMENS [ Siemens Semiconductor Group ]
