Rev.2.4
_00
AC Electrical Characteristics
Table 7
Measurement Conditions
2-WIRE REAL-TIME CLOCK
S-35390A
V
DD
Input pulse voltage
Input pulse rise/fall time
Output determination voltage
Output load
V
IH
= 0.9
×
V
DD
, V
IL
= 0.1
×
V
DD
20 ns
V
OH
= 0.5
×
V
DD
, V
OL
= 0.5
×
V
DD
100 pF
+
pull-up resistor 1 k
Ω
R
=
1 kΩ
SDA
C = 100 pF
Remark
The power supplies of the IC
and load have the same
electrical potential.
Output Load Circuit
Figure 8
Table 8
AC Electrical Characteristics
Parameter
SCL clock frequency
SCL clock low time
SCL clock high time
SDA output delay time
*1
Start condition setup time
Start condition hold time
Data input setup time
Data input hold time
Stop condition setup time
SCL, SDA rise time
SCL, SDA fall time
Bus release time
Noise suppression time
Symbol
f
SCL
t
LOW
t
HIGH
t
PD
t
SU.STA
t
HD.STA
t
SU.DAT
t
HD.DAT
t
SU.STO
t
R
t
F
t
BUF
t
I
V
DD
Min.
0
4.7
4
*2
≥
1.3 V
Typ.
Max.
−
−
−
−
−
−
−
−
−
−
−
−
−
100
−
4.7
4
250
0
4.7
−
−
3.5
−
−
−
−
V
DD
Min.
0
1.3
0.6
*2
−
0.6
0.6
100
0
0.6
−
−
4.7
−
1
0.3
−
−
100
−
−
1.3
−
(Ta =
−
40 to +85
°
C)
≥
3.0 V
Unit
Typ.
Max.
−
400
kHz
µs
−
−
µs
−
−
0.9
µs
−
µs
−
−
µs
−
−
−
−
ns
µs
−
−
µs
−
−
0.3
µs
−
0.3
µs
−
µs
−
−
50
ns
−
*1
. Since the output format of the SDA pin is Nch open-drain output, SDA output delay time is determined by the values of
the load resistance (R
L
) and load capacity (C
L
) outside the IC. Therefore, use this value only as a reference value.
*2.
Regarding the power supply voltage, refer to
“ Recommended Operation Conditions”
.
t
F
t
HIGH
t
LOW
t
R
SCL
t
HD.DAT
t
SU.DAT
t
SU.STO
t
SU.STA
t
HD.STA
SDA
(Input from S-35390A)
t
PD
t
BUF
SDA
(Output from S-35390A)
Figure 9
Bus Timing
Seiko Instruments Inc.
7
SII [ SEIKO INSTRUMENTS INC ]
