ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
Rev.3.3_00
S-809xxC Series
Standard Circuit
R*1
100 kΩ
VDD
VSS
CD
OUT
*2
CD
*1. R is unnecessary for CMOS output products.
*2. The delay capacitor (CD) should be connected directly to the CD pin and to the VSS pin.
Figure 18
Caution The above connection diagram and constant will not guarantees successful operation.
Perform through evaluation using the actual application to set the constant.
Technical Terms
1. Detection Voltage (−VDET), Release Voltage (+VDET
)
The detection voltage (−VDET) is a voltage at which the output turns to low. This detection voltage varies
slightly among products of the same specification. The variation of detection voltage between the
specified minimum (−VDET) Min. and maximum (−VDET) Max. is called the detection voltage range (Refer to
Figure 19).
Example: For the S-80927CN, detection voltage lies in the range of 2.646≤(−VDET) ≤ 2.754.
This means that some S-80927CNs have 2.646 V for −VDET and some have 2.754 V.
The release voltage (+VDET) is a voltage at which the output turns to high. This release voltage varies
slightly among products of the same specification. The variation of release voltage between the specified
minimum (+VDET) Min. and maximum (+VDET) Max. is called the release voltage range (Refer to Figure 20).
The range is calculated from the actual detection voltage (−VDET) of a product and is expressed by
−VDET×1.03≤+VDET≤−VDET×1.08 for S-80913 to S-80914, and by −VDET×1.03≤+VDET≤−VDET ×1.07 for S-
80915 to S-80960.
Example: For the S-80927CN, the release voltage lies in the range of 2.725≤(+VDET)≤ 2.947.
This means that some S-80927CNs have 2.725 V for +VDET and some have 2.947 V.
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Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
