ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
Rev.3.3
_00
S-809xxC Series
Operation
1. Basic Operation: CMOS Output (Active Low)
1-1.
When the power supply voltage (V
DD
) is higher than the release voltage (+V
DET
), the Nch transistor is
OFF and the Pch transistor is ON to provide V
DD
(high) at the output. Since the Nch transistor N1 in
(R
B
+
R
C
)
•
V
DD
.
Figure 14
is OFF, the comparator input voltage is
R
A
+
R
B
+
R
C
1-2.
When the V
DD
goes below
+V
DET
, the output provides the V
DD
level, as long as the V
DD
remains above
the detection voltage
−V
DET
. When the V
DD
falls below
−V
DET
(point A in
Figure 15),
the Nch
transistor becomes ON, the Pch transistor becomes OFF, and the V
SS
level appears at the output. At
this time the Nch transistor N1 in
Figure 14
becomes ON, the comparator input voltage is changed to
R
B
•
V
DD
.
R
A
+
R
B
1-3.
When the V
DD
falls below the minimum operating voltage, the output becomes undefined, or goes to
the V
DD
when the output is pulled up to the V
DD
.
1-4.
The V
SS
level appears when the V
DD
rises above the minimum operating voltage. The V
SS
level still
appears even when the V
DD
surpasses
−V
DET
, as long as it does not exceed the release voltage
+V
DET
.
1-5.
When V
DD
rises above
+V
DET
(point B in
Figure 15),
the Nch transistor becomes OFF, and the Pch
transistor becomes ON, and V
DD
appears at the output after the delay time (t
D
) counted by the delay
circuit.
V
DD
R
A
*1
*1
+
−
R
B
V
REF
Delay
circuit
Pch
OUT
*1
*1
Nch
R
C
N1
CD
C
D
V
SS
*1.
Parasitic diode
Figure 14 Operation 1
12
Seiko Instruments Inc.
SII [ SEIKO INSTRUMENTS INC ]
