Rev.2.1
_00
Block Diagram
Memory array
Address
decoder
CMOS SERIAL E
2
PROM
S-93A46A/56A/66A
VCC
GND
Data register
DI
Mode decode logic
CS
Clock pulse
monitoring circuit
Output buffer
DO
Voltage detector
SK
Clock generator
Figure 2
Instruction Sets
1. S-93A46A
Table 2
Instruction
SK input clock
READ (Read data)
WRITE (Write data)
ERASE (Erase data)
WRAL (Write all)
ERAL (Erase all)
EWEN (Write enable)
EWDS (Write disable)
Start Bit
1
1
1
1
1
1
1
1
Operation Code
2
1
0
1
0
0
0
0
3
0
1
1
0
0
0
0
4
A5
A5
A5
0
1
1
0
5
A4
A4
A4
1
0
1
0
Address
6
A3
A3
A3
x
x
x
x
7
A2
A2
A2
x
x
x
x
8
A1
A1
A1
x
x
x
x
9
A0
A0
A0
x
x
x
x
Data
10 to 25
D15 to D0 output
*1
D15 to D0 input
D15 to D0 input
*1.
When the 16-bit data in the specified address has been output, the data in the next address is output.
Remark
x: Doesn’t matter
Seiko Instruments Inc.
3
SII [ SEIKO INSTRUMENTS INC ]
