C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
21. JTAG (IEEE 1149.1)
Each MCU has an on-chip JTAG interface and logic to support boundary scan for production and in-system testing,
Flash read and write operations, and non-intrusive in-circuit debug. The JTAG interface is fully compliant with the
IEEE 1149.1 specification. Refer to this specification for detailed descriptions of the Test Interface and Boundary-
Scan Architecture. Access of the JTAG Instruction Register (IR) and Data Registers (DR) are as described in the
Test Access Port and Operation of the IEEE 1149.1 specification.
The JTAG interface is via four dedicated pins on the MCU, which are TCK, TMS, TDI, and TDO. These pins are
all 5V tolerant.
Through the 16-bit JTAG Instruction Register (IR), any of the eight instructions shown in Figure 21.1 can be
commanded. There are three Data Registers (DR’s) associated with JTAG Boundary-Scan, and four associated with
Flash read/write operations on the MCU.
Figure 21.1. IR: JTAG Instruction Register
Reset Value
0x0004
Bit15
Bit0
IR value
0x0000
0x0002
0x0004
0xFFFF
0x0082
0x0083
0x0084
0x0085
Instruction
EXTEST
SAMPLE/
PRELOAD
IDCODE
BYPASS
Flash Control
Flash Data
Flash Address
Flash Scale
Description
Selects the Boundary Data Register for control and observability of all
device pins
Selects the Boundary Data Register for observability and presetting the
scan-path latches
Selects device ID Register
Selects Bypass Data Register
Selects FLASHCON Register to control how the interface logic responds to
reads and writes to the FLASHDAT Register
Selects FLASHDAT Register for reads and writes to the Flash memory
Selects FLASHADR Register which holds the address of all Flash read,
write, and erase operations
Selects FLASHSCL Register which controls the prescaler used to generate
timing signals for Flash operations
Rev. 1.7
164
SILABS [ SILICON LABORATORIES ]
