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C8051F363 参数 Datasheet PDF下载

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型号: C8051F363
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内容描述: 混合信号ISP功能的Flash MCU系列 [Mixed Signal ISP Flash MCU Family]
分类和应用:
文件页数/大小: 288 页 / 2659 K
品牌: SILICON [ SILICON ]
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C8051F360/1/2/3/4/5/6/7/8/9  
9.4. Memory Organization  
The memory organization of the CIP-51 System Controller is similar to that of a standard 8051. There are  
two separate memory spaces: program memory and data memory. Program and data memory share the  
same address space but are accessed via different instruction types. There are 256 bytes of internal data  
memory and 32k bytes (C8051F360/1/2/3/4/5/6/7) or 16k bytes (C8051F368/9) of internal program mem-  
ory address space implemented within the CIP-51. The CIP-51 memory organization is shown in  
Figure 9.2.  
PROGRAM MEMORY  
C8051F360/1/2/3/4/5/6/7  
RESERVED  
DATA MEMORY  
INTERNAL DATA ADDRESS SPACE  
0xFF  
Upper 128 RAM  
(Indirect Addressing  
Only)  
Special Function  
Register's  
(Direct Addressing Only)  
0x80  
0x7F  
0x7C00  
0x7BFF  
(Direct and Indirect  
Addressing)  
Lower 128 RAM  
(Direct and Indirect  
Addressing)  
0x30  
0x2F  
FLASH  
Bit Addressable  
(In-System  
Programmable in 1024  
Byte Sectors)  
0x20  
0x1F  
General Purpose  
Registers  
0x00  
0x0000  
EXTERNAL DATA ADDRESS SPACE  
C8051F368/9  
RESERVED  
0xFFFF  
0x4000  
0x3FFF  
Same 1024 bytes as from  
0x0000 to 0x03FF, wrapped  
on 1024-byte boundaries  
FLASH  
(In-System  
Programmable in 1024  
Byte Sectors)  
0x0400  
0x03FF  
XRAM - 1024 Bytes  
(accessable using MOVX  
instruction)  
0x0000  
0x0000  
Figure 9.2. Memory Map  
9.4.1. Program Memory  
The CIP-51 core has a 64 kB program memory space. The C8051F360/1/2/3/4/5/6/7 implement 32 kB of  
this program memory space as in-system, re-programmable Flash memory, organized in a contiguous  
block from addresses 0x0000 to 0x7BFF. Addresses above 0x7BFF are reserved on the 32 kB devices.  
The C8051F368/9 implement 16 kB of Flash from addresses 0x0000 to 0x3FFF.  
Program memory is normally assumed to be read-only. However, the CIP-51 can write to program memory  
by setting the Program Store Write Enable bit (PSCTL.0) and using the MOVX instruction. This feature pro-  
vides a mechanism for the CIP-51 to update program code and use the program memory space for non-  
volatile data storage. Refer to Section “13. Flash Memory” on page 135 for further details.  
86  
Rev. 1.0