C8051F310/1/2/3/4/5/6/7
any other reset source. For example, if the V
DD
monitor is enabled and a software reset is performed, the
V
DD
monitor will still be enabled after the reset.
Important Note:
The V
DD
monitor must be enabled before it is selected as a reset source. Selecting the
V
DD
monitor as a reset source before it is enabled and stabilized may cause a system reset. The proce-
dure for configuring the V
DD
monitor as a reset source is shown below:
Step 1. Enable the V
DD
monitor (VDMEN bit in VDM0CN = ‘1’).
Step 2. Wait for the V
DD
monitor to stabilize (see Table 9.1 for the V
DD
Monitor turn-on time).
Note: This delay should be omitted if software contains routines that erase or write Flash
memory.
Step 3. Select the V
DD
monitor as a reset source (PORSF bit in RSTSRC = ‘1’).
See Figure 9.2 for V
DD
monitor timing; note that the reset delay is not incurred after a V
DD
monitor reset.
See Table 9.1 for complete electrical characteristics of the V
DD
monitor.
SFR Definition 9.1. VDM0CN: V
DD
Monitor Control
R/W
Bit7
R
Bit6
R
Bit5
R
Bit4
R
Bit3
R
Bit2
R
Bit1
R
Bit0
SFR Address:
0xFF
Reset Value
VDMEN VDDSTAT Reserved Reserved Reserved Reserved Reserved Reserved
Variable
VDMEN: V
DD
Monitor Enable.
This bit is turns the V
DD
monitor circuit on/off. The V
DD
Monitor cannot generate system
resets until it is also selected as a reset source in register RSTSRC (Figure 9.2). The V
DD
Monitor must be allowed to stabilize before it is selected as a reset source.
Selecting the
V
DD
monitor as a reset source before it has stabilized may generate a system reset.
See Table 9.1 for the minimum V
DD
Monitor turn-on time.
0: V
DD
Monitor Disabled.
1: V
DD
Monitor Enabled.
Bit6:
V
DD
STAT: V
DD
Status.
This bit indicates the current power supply status (V
DD
Monitor output).
0: V
DD
is at or below the V
DD
monitor threshold.
1: V
DD
is above the V
DD
monitor threshold.
Bits5–0: Reserved. Read = Variable. Write = don’t care.
Bit7:
9.3.
External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Table 9.1 for complete RST pin spec-
ifications. The PINRSF flag (RSTSRC.0) is set on exit from an external reset.
Rev. 1.7
107
SILABS [ SILICON LABORATORIES ]
