C8051F310/1/2/3/4/5/6/7
Table 9.1. Reset Electrical Characteristics
–40 to +85 °C unless otherwise specified.
Parameter
Conditions
OL = 8.5 mA, VDD = 2.7 to 3.6 V
Min
Typ
Max
Units
I
RST Output Low Voltage
—
—
0.6
V
0.7 x
VDD
RST Input High Voltage
—
—
—
V
0.3 x
VDD
RST Input Low Voltage
—
RST = 0.0 V
—
25
40
µA
V
RST Input Pullup Current
VDD Monitor Threshold (VRST
)
2.40
2.55
2.70
Time from last system clock rising
edge to reset initiation
Missing Clock Detector Timeout
Reset Time Delay
100
5.0
15
220
600
µs
µs
µs
Delay between release of any
reset source and code execution
at location 0x0000
—
—
Minimum RST Low Time to
Generate a System Reset
—
—
VDD Monitor Turn-on Time
100
—
—
20
—
—
50
1
µs
µA
ms
VDD Monitor Supply Current
VDD Ramp Time
VDD = 0 V to VDD = 2.7 V
—
110
Rev. 1.7
SILICON [ SILICON ]
