C8051F310 参数 Datasheet PDF下载

C8051F310/1/2/3/4/5/6/7

1.8.

Comparators

C8051F31x devices include two on-chip voltage comparators that are enabled/disabled and configured via

user software. Port I/O pins may be configured as comparator inputs via a selection mux. Two comparator

outputs may be routed to a Port pin if desired: a latched output and/or an unlatched (asynchronous) output.

Comparator response time is programmable, allowing the user to select between high-speed and low-

power modes. Positive and negative hysteresis are also configurable.

Comparator interrupts may be generated on rising, falling, or both edges. When in IDLE mode, these inter-

rupts may be used as a “wake-up” source. Comparator0 may also be configured as a reset source.

CP0EN

CPT0CN

CP0OUT

CP0RIF

CP0FIF

CP0HYP1

CP0HYP0

CP0HYN1

CP0HYN0

VDD

CPT0MX

CMX0N1

CMX0N0

CP0

Interrupt

CMX0P1

CMX0P0

P1.0

P1.4

P2.0

P2.4

CP0 +

Interrupt

Logic

CP0

Rising-edge

CP0

Falling-edge

+

D

SET

CP0

Q

D

SET

Q

-

P1.1

P1.5

P2.1

P2.5

CP0 -

GND

Reset

Decision

Tree

CP0RIE

CP0FIE

CLR

Q

CLR

Q

Crossbar

(SYNCHRONIZER)

CP0A

CPT0MD

CP0MD1

CP0MD0

Figure 1.16. Comparator0 Block Diagram

34

Rev. 1.7