C8051F310/1/2/3/4/5/6/7
8.
CIP-51 Microcontroller
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in
an enhanced full-duplex UART (see description
in
an Enhanced SPI (see description in
256 bytes of internal RAM, 128 byte
Special Function Register (SFR) address space (Section
and 29 Port I/O (see description in
The CIP-51 also includes on-chip debug hardware (see description in
and interfaces
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 8.1 for a block diagram).
The CIP-51 includes the following features:
- Fully Compatible with MCS-51 Instruction
Set
- 25 MIPS Peak Throughput with 25 MHz
Clock
- 0 to 25 MHz Clock Frequency
- 256 Bytes of Internal RAM
-
-
-
-
-
-
29 Port I/O
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
DATA BUS
D8
D8
D8
D8
D8
ACCUMULATOR
B REGISTER
STACK POINTER
DATA BUS
TMP1
TMP2
PSW
ALU
D8
D8
SRAM
ADDRESS
REGISTER
D8
SRAM
(256 X 8)
D8
DATA BUS
SFR_ADDRESS
BUFFER
D8
DATA POINTER
D8
D8
SFR
BUS
INTERFACE
SFR_CONTROL
SFR_WRITE_DATA
SFR_READ_DATA
PC INCREMENTER
DATA BUS
PROGRAM COUNTER (PC)
D8
MEM_ADDRESS
MEM_CONTROL
PRGM. ADDRESS REG.
A16
MEMORY
INTERFACE
MEM_WRITE_DATA
MEM_READ_DATA
PIPELINE
RESET
CLOCK
STOP
IDLE
POWER CONTROL
REGISTER
D8
D8
CONTROL
LOGIC
INTERRUPT
INTERFACE
SYSTEM_IRQs
EMULATION_IRQ
D8
Figure 8.1. CIP-51 Block Diagram
Rev. 1.7
79
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