C8051F340/1/2/3/4/5/6/7
USB Register Definition 16.13. CMINT: USB0 Common Interrupt
R
-
R
-
R
-
R
-
R
R
R
R
Reset Value
SOF
Bit3
RSTINT RSUINT SUSINT 00000000
Bit7
Bit6
Bit5
Bit4
Bit2
Bit1
Bit0
USB Address:
0x06
Bits7–4: Unused. Read = 0000b; Write = don’t care.
Bit3:
SOF: Start of Frame Interrupt
Set by hardware when a SOF token is received. This interrupt event is synthesized by hard-
ware: an interrupt will be generated when hardware expects to receive a SOF event, even if
the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
Bit2:
Bit1:
RSTINT: Reset Interrupt-pending Flag
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
RSUINT: Resume Interrupt-pending Flag
Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend
mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
Bit0:
SUSINT: Suspend Interrupt-pending Flag
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hard-
ware when Suspend signaling is detected on the bus. This bit is cleared when software
reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.
182
Rev. 1.0
SILICON [ SILICON ]
