C8051F413 参数 Datasheet PDF下载

C8051F410/1/2/3

The following steps can be used to read the current timer value:

Step 1. Write ‘1’ to RTC0CAP. This will transfer the contents of the timer to the CAPTUREn

registers (the LSB of the smaRTClock timer will be found in CAPTURE0.1).

Step 2. Poll RTC0CAP until it is cleared to ‘0’ by hardware.

Step 3. A snapshot of the timer value can be read from the CAPTUREn registers

20.3.2. Setting a smaRTClock Alarm

The smaRTClock Alarm function compares the 47-bit value of smaRTClock Timer to the value of the

ALARMn registers. An alarm event is triggered if the smaRTClock timer is

greater than or equal to

the

ALARMn registers. If the smaRTClock Interrupt is enabled, the CIP-51 will vector to the smaRTClock Inter-

rupt Service Routine when an alarm event occurs. If smaRTClock is enabled as a reset source, the MCU

will be reset when an alarm event occurs. Also, the internal oscillator will awaken from suspend mode on a

smaRTClock alarm event.

The following steps can be used to set up a smaRTClock Alarm:

Step 1. Disable smaRTClock Alarm Events (RTC0AEN = 0).

Step 2. Set the ALARMn registers to the desired value.

Step 3. Enable smaRTClock Alarm Events (RTC0AEN = 1).

Note:

When an alarm event occurs and smaRTClock interrupts are enabled, software should clear the

ALRM bit and set the ALARM5-0 registers to the maximum possible value to avoid continuous alarm inter-

rupts.

Internal Register Definition 20.6. CAPTUREn: smaRTClock Timer Capture

R/W

Bit7

R/W

Bit6

R/W

Bit5

R/W

Bit4

R/W

Bit3

R/W

Bit2

R/W

Bit1

R/W

Bit0

Reset Value

11111111

smaRTClock Addresses: CAPTURE0: 0x00; CAPTURE1: 0x01; CAPTURE2: 0x02; CAPTURE3: 0x03; CAPTURE4: 0x04; CAPTURE5:

0x05

Note: These registers are not SFRs. They can only be accessed indirectly through RTC0ADR and RTC0DAT.

Bits 7–0: CAPTUREn: smaRTClock Set/Capture Value.

These 6 registers (CAPTURE5–CAPTURE0) are used to read or set the 47-bit smaRTClock

timer. Data is transferred to or from the smaRTClock timer when the RTC0SET or RTC0CAP

bits are set.

Note:

The LSB of CAPTURE0 is not used. The LSB of the 47-bit smaRTClock timer will appear in

CAPTURE0.1.

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Rev. 1.0