C8051F410/1/2/3
; Enable the smaRTClock
mov RTC0ADR, #06h ; address the RTC0CN register
mov RTC0DAT, #080h ; enable the smaRTClock
L0:mov A, RTC0ADR
jb ACC.7, L0
; poll on the BUSY bit
; Write to the smaRTClock RAM
mov RTC0ADR, #0Eh; address the RAMADDR register
mov RTC0DAT, #20h; write the address of 0x20 to RAMADDR
L1:mov A, RTC0ADR
jb ACC.7, L1
; poll on the BUSY bit
mov RTC0ADR, #0Fh; address the RAMDATA register
mov RTC0DAT, #0A5h; write 0xA5 to RAM address 0x20
L2: mov A, RTC0ADR
jb ACC.7, L2
; poll on the BUSY bit
; Read from the smaRTClock RAM
mov RTC0ADR, #0Eh; address the RAMADDR register
mov RTC0DAT, #20h; write the address of 0x20 to RAMADDR
L3:mov A, RTC0ADR
jb ACC.7, L3
; poll on the BUSY bit
mov RTC0ADR, #0Fh
orl RTC0ADR, #80h
L4: mov A, RTC0ADR
jb ACC.7, L4
; address the RAMDATA register
; initiate a read of the RAMDATA register
; poll on the BUSY bit
movR0, #80h
mov@R0, RTC0DAT
; read the value of RAM address 0x20 into
; the 128-byte internal RAM
To reduce the number of instructions necessary to read and write sections of the 64-byte RAM, the
RAMADDR register automatically increments after each write or read. The following C example initializes
the entire 64-byte RAM to 0xA5 and copies this value from the RAM to an array using the auto-increment
feature:
// in 'C':
unsigned char RAM_data[64] = 0x00;
unsigned char addr;
// Unlock smaRTClock, enable smaRTClock
// Write to the entire smaRTClock RAM
RTC0ADR = 0x0E;// address the RAMADDR register
RTC0DAT = 0x00;// write the address of 0x00 to RAMADDR
while ((RTC0ADR & 0x80) == 0x80);
// poll on the BUSY bit
RTC0ADR = 0x0F;// address the RAMDATA register
for (addr = 0; addr < 64; addr++)
{
RTC0DAT = 0xA5; // write 0xA5 to every RAM address
while ((RTC0ADR & 0x80) == 0x80);// poll on the BUSY bit
}
// Read from the entire smaRTClock RAM
RTC0ADR = 0x0E;// address the RAMADDR register
Rev. 1.0
189
SILICON [ SILICON ]
