C8051F80x-83x
SFR Definition 21.1. VDM0CN: V
DD
Monitor Control
Bit
Name
Type
Reset
7
VDMEN
R/W
Varies
6
VDDSTAT
R
Varies
R
Varies
R
Varies
R
Varies
Function
V
DD
Monitor Enable.
This bit turns the V
DD
monitor circuit on/off. The V
DD
Monitor cannot generate sys-
tem resets until it is also selected as a reset source in register RSTSRC (SFR Def-
DD
monitor as a reset source before it has stabilized
may generate a system reset. In systems where this reset would be undesirable, a
delay should be introduced between enabling the V
DD
Monitor and selecting it as a
reset source. After a power-on reset, the VDD monitor is enabled, and this bit will
read 1. The state of this bit is sticky through any other reset source.
0: V
DD
Monitor Disabled.
1: V
DD
Monitor Enabled.
6
VDDSTAT
V
DD
Status.
This bit indicates the current power supply status (V
DD
Monitor output).
0: V
DD
is at or below the V
DD
monitor threshold.
1: V
DD
is above the V
DD
monitor threshold.
5:0
Unused
Read = Varies; Write = Don’t care.
R
Varies
R
Varies
R
Varies
5
4
3
2
1
0
SFR Address = 0xFF
Bit
Name
7
VDMEN
21.3. External Reset
The external RST pin provides a means for external circuitry to force the device into a reset state. Assert-
ing an active-low signal on the RST pin generates a reset; an external pullup and/or decoupling of the RST
pin may be necessary to avoid erroneous noise-induced resets. See Section “7. Electrical Characteristics”
nal reset.
21.4. Missing Clock Detector Reset
The Missing Clock Detector (MCD) is a one-shot circuit that is triggered by the system clock. If the system
clock remains high or low for more than the MCD timeout, the one-shot will time out and generate a reset.
After a MCD reset, the MCDRSF flag (RSTSRC.2) will read 1, signifying the MCD as the reset source; oth-
erwise, this bit reads 0. Writing a 1 to the MCDRSF bit enables the Missing Clock Detector; writing a 0 dis-
ables it. The state of the RST pin is unaffected by this reset.
126
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
