C8051F80x-83x
SFR Definition 23.2. XBR1: Port I/O Crossbar Register 1
Bit
7
6
5
4
3
2
1
0
WEAKPUD XBARE
T1E
T0E
ECIE
PCA0ME[1:0]
R/W R/W
Name
Type
Reset
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
0
0
0
SFR Address = 0xE2
Bit
Name
Function
7
WEAKPUD Port I/O Weak Pullup Disable.
0: Weak Pullups enabled (except for Ports whose I/O are configured for analog
mode).
1: Weak Pullups disabled.
6
5
4
3
2
XBARE
T1E
Crossbar Enable.
0: Crossbar disabled.
1: Crossbar enabled.
T1 Enable.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
T0E
T0 Enable.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
ECIE
PCA0 External Counter Input Enable.
0: ECI unavailable at Port pin.
1: ECI routed to Port pin.
Unused
Read = 0b; Write = Don’t Care.
1:0 PCA0ME[1:0] PCA Module I/O Enable Bits.
00: All PCA I/O unavailable at Port pins.
01: CEX0 routed to Port pin.
10: CEX0, CEX1 routed to Port pins.
11: CEX0, CEX1, CEX2 routed to Port pins.
Rev. 1.0
149
SILICON [ SILICON ]
