C8051F80x-83x
25. Enhanced Serial Peripheral Interface (SPI0)
The Enhanced Serial Peripheral Interface (SPI0) provides access to a flexible, full-duplex synchronous
serial bus. SPI0 can operate as a master or slave device in both 3-wire or 4-wire modes, and supports mul-
tiple masters and slaves on a single SPI bus. The slave-select (NSS) signal can be configured as an input
to select SPI0 in slave mode, or to disable Master Mode operation in a multi-master environment, avoiding
contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can
also be configured as a chip-select output in master mode, or disabled for 3-wire operation. Additional gen-
eral purpose port I/O pins can be used to select multiple slave devices in master mode.
SFR Bus
SPI0CKR
SCR7
SCR6
SCR5
SCR4
SCR3
SCR2
SCR1
SCR0
SPI0CFG
SPIBSY
MSTEN
CKPHA
CKPOL
SLVSEL
NSSIN
SRMT
RXBMT
SPI0CN
SPIF
WCOL
MODF
RXOVRN
NSSMD1
NSSMD0
TXBMT
SPIEN
SYSCLK
Clock Divide
Logic
SPI CONTROL LOGIC
Data Path
Control
Pin Interface
Control
SPI IRQ
Tx Data
MOSI
SPI0DAT
Transmit Data Buffer
Pin
Control
Logic
SCK
Shift Register
7 6 5 4 3 2 1 0
Rx Data
MISO
C
R
O
S
S
B
A
R
Port I/O
Receive Data Buffer
NSS
Write
SPI0DAT
Read
SPI0DAT
SFR Bus
Figure 25.1. SPI Block Diagram
Rev. 1.0
167
SILABS [ SILICON LABORATORIES ]
