C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F826, ‘F829: 8 kB
‘F832, ‘F835: 4 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
SYSCLK
Analog Peripherals
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
External
Clock
Circuit
XTAL1
XTAL2
VDD
(‘F826, ‘F832 Only)
VREG Output
VREF
A
M
U
X
10-bit
500 ksps
ADC
VDD
12 Channels
System Clock
Configuration
Temp Sensor
Figure 1.9. C8051F826, C8051F829, C8051F832, C8051F835 Block Diagram
24
Rev. 1.0
SILICON [ SILICON ]
