C8051F80x-83x
3. Pin Definitions
Table 3.1. Pin Definitions for the C8051F80x-83x
Name
GND
Pin
QSOP-24
5
Pin
QFN-20
2
Pin
SOIC-16
4
Type
Description
Ground.
This ground connection is required. The center
pad may optionally be connected to ground as
well on the QFN-20 packages.
Power Supply Voltage.
D I/O
Device Reset. Open-drain output of internal
POR or V
DD
monitor. An external source can ini-
tiate a system reset by driving this pin low for at
least 10 µs.
Clock signal for the C2 Debug Interface.
Bi-directional data signal for the C2 Debug Inter-
face. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
Bi-directional data signal for the C2 Debug Inter-
face. Shared with P2.0 on 20-pin packaging and
P2.4 on 24-pin packaging.
V
DD
RST/
6
7
3
4
5
6
C2CK
P2.0/
8
5
7
D I/O
D I/O
C2D
D I/O
P0.0/
VREF
P0.1
P0.2/
XTAL1
P0.3/
XTAL2
4
1
3
D I/O or Port 0.0.
A In
A In
External VREF input.
3
2
20
19
2
1
D I/O or Port 0.1.
A In
D I/O or Port 0.2.
A In
A In
External Clock Input. This pin is the external
oscillator return for a crystal or resonator.
23
18
16
D I/O or Port 0.3.
A In
A I/O or External Clock Output. For an external crystal or
resonator, this pin is the excitation driver. This
D In
pin is the external clock input for CMOS, capaci-
tor, or RC oscillator configurations.
P0.4
22
17
15
D I/O or Port 0.4.
A In
28
Rev. 1.0
SILABS [ SILICON LABORATORIES ]
