C8051F80x-83x
CIP-51 8051
Port I/O Configuration
Controller Core
Power On
Reset
P0.0/VREF
P0.1/AGND
P0.2/XTAL1
P0.3/XTAL2
P0.4/TX
P0.5/RX
P0.6/CNVSTR
P0.7
Digital Peripherals
Flash Memory
‘F800/6: 16 kB
‘F812/8: 8 kB
UART
Reset
Port 0
Drivers
Timers
0, 1
256 Byte RAM
Debug /
Programming
Hardware
RST/C2CK
256 Byte XRAM
Timer 2 /
Priority
RTC
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
Crossbar
P2.0/C2D
Decoder
PCA/
WDT
Port 1
Drivers
SMBus
Peripheral
Power
SFR
Bus
SPI
Core Power
P2.0/C2D
VDD
GND
Regulator
Crossbar Control
Port 2
Drivers
Analog
Peripherals
SYSCLK
16 Channels
Capacitive
Sense
A
M
U
X
Precision
Internal
Oscillator
+
-
VREG Output
Comparator
VDD
External
Clock
Circuit
XTAL1
XTAL2
(‘F800, ‘F812 Only)
VREG Output
VREF
A
M
U
X
10-bit
VDD
16 Channels
500 ksps
ADC
System Clock
Configuration
Temp Sensor
Figure 1.1. C8051F800, C8051F806, C8051F812, C8051F818 Block Diagram
16
Rev. 1.0
SILICON [ SILICON ]
