C8051T600/1/2/3/4/5/6
26.3.5. 8-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 8-bit PWM mode is varied using the module's PCA0CPLn Cap-
ture/Compare register. When the value in the low byte of the PCA counter/timer (PCA0L) is equal to the
value in PCA0CPLn, the output on the CEXn pin will be set. When the count value in PCA0L overflows, the
CEXn output will be reset (see Figure 26.8). Also, when the counter/timer low byte (PCA0L) overflows from
0xFF to 0x00, PCA0CPLn is reloaded automatically with the value stored in the module’s Capture/Com-
pare high byte (PCA0CPHn) without software intervention. Setting the ECOMn and PWMn bits in the
PCA0CPMn register enables 8-Bit Pulse Width Modulator mode. If the MATn bit is set to 1, the CCFn flag
for the module will be set each time an 8-bit comparator match (rising edge) occurs. The duty cycle for 8-
Bit PWM Mode is given in Equation 26.2.
Important Note about Capture/Compare Registers:
When writing a 16-bit value to the PCA0 Cap-
ture/Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the
ECOMn bit to 0; writing to PCA0CPHn sets ECOMn to 1.
256 –
PCA0CPHn
-
Duty Cycle = --------------------------------------------------
256
Equation 26.2. 8-Bit PWM Duty Cycle
Using Equation 26.2, the largest duty cycle is 100% (PCA0CPHn = 0), and the smallest duty cycle is
0.39% (PCA0CPHn = 0xFF). A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
Write to
PCA0CPLn
Reset
Write to
PCA0CPHn
0
ENB
PCA0CPHn
ENB
1
COVF
PCA0CPMn
P ECCMT P E
WC A A A O WC
MO P P T GMC
1 MP N n n n F
6 n n n
n
n
0
0 0 x 0
x
Enable
PCA0CPLn
8-bit
Comparator
match
S
SET
Q
CEXn
Crossbar
Port I/O
R
PCA Timebase
CLR
Q
PCA0L
Overflow
Figure 26.8. PCA 8-Bit PWM Mode Diagram
168
Rev. 1.2
SILABS [ SILICON LABORATORIES ]
