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SI3056SSI2-EVB 参数 Datasheet PDF下载

SI3056SSI2-EVB图片预览
型号: SI3056SSI2-EVB
PDF下载: 下载PDF文件 查看货源
内容描述: 全球串行接口直接访问安排 [GLOBAL SERIAL INTERFACE DIRECT ACCESS ARRANGEMENT]
分类和应用:
文件页数/大小: 94 页 / 1395 K
品牌: SILICON [ SILICON ]
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Si3056  
Si3018/19/10  
Table 4. AC Characteristics (Continued)  
(VD = 3.0 to 3.6 V, TA = 0 to 70 °C; see Figure 17 on page 18)  
Parameter  
Symbol  
Test Condition  
Min  
Typ  
Max  
Unit  
Receive Total Harmonic  
THD  
ILIM = 0, DCV = 00, DCR = 0,  
–78  
dB  
8,9  
Distortion  
I = 20 mA, MINI = 11  
L
Receive Total Harmonic  
THD  
ILIM = 1, DCV = 11, DCR = 0,  
–78  
50  
dB  
dB  
8,9  
Distortion  
I = 50 mA, MINI = 00  
L
Dynamic Range (caller ID  
DR  
VIN = 1 kHz, –13 dBFS  
CID  
10,7  
mode)  
10  
Caller ID Full Scale Level  
AOUT Low Level Current  
AOUT High Level Current  
V
6
10  
10  
V
PEAK  
CID  
mA  
mA  
Notes:  
1. See Figure 26 on page 37.  
2. Measured at TIP and RING with 600 termination at 1 kHz, as shown in Figure 1.  
3. With FULL = 1, the transmit and receive full scale level of +3.2 dBm can be achieved with a 600 ac termination, while  
the transmit and receive level in dBm varies with reference impedance, the DAA will transmit and receive 1 dBV into all  
reference impedances in “FULL” mode. With FULL2 = 1, the transmit and receive full scale level of +6.0 dBm can be  
achieved with a 600 ac termination. In “FULL2” mode, the DAA will transmit and receive +1.5 dBV into all reference  
impedances.  
4. Receive full scale level produces –0.9 dBFS at SDO.  
5. DR = 20 x log (RMS VFS/RMS VIN).+ 20 x log (RMS VIN/RMS noise). The RMS noise measurement excludes  
harmonics. VFS is the 0 dBm full-scale level.  
6. Measurement is 300 to 3400 Hz. Applies to both transmit and receive paths. VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.  
7. When using the Si3010 line-side, the typical DR values will be approximately 10 dB lower.  
8. THD = 20 x log (RMS distortion/RMS signal). VIN = 1 kHz, –3 dBFS, Fs = 10300 Hz.  
9. When using the Si3010 line-side, the typical THD values will be approximately 10 dB higher.  
10. DRCID = 20 x log (RMS VCID/RMS VIN) + 20 x log(RMS VIN/RMS noise). VCID is the 6 V full-scale level for the typical  
application circuit in Figure 17. With the enhanced CID circuit, the VCID full-scale level is 1.5 V peak, and DRCID  
increases to 62 dB.  
11. Available on the Si3019 line-side device only.  
Rev. 1.05  
9